From patchwork Mon Sep 26 18:44:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylvain Lemieux X-Patchwork-Id: 9351187 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F37266077B for ; Mon, 26 Sep 2016 18:45:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E628F28A58 for ; Mon, 26 Sep 2016 18:45:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D97F028AD0; Mon, 26 Sep 2016 18:45:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,RCVD_IN_DNSWL_HI,RCVD_IN_SORBS_SPAM, RCVD_IN_SORBS_WEB,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8EF2128A58 for ; Mon, 26 Sep 2016 18:44:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161206AbcIZSox (ORCPT ); Mon, 26 Sep 2016 14:44:53 -0400 Received: from mail-io0-f193.google.com ([209.85.223.193]:36206 "EHLO mail-io0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1035090AbcIZSow (ORCPT ); Mon, 26 Sep 2016 14:44:52 -0400 Received: by mail-io0-f193.google.com with SMTP id z135so11497363ioe.3 for ; Mon, 26 Sep 2016 11:44:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=6IYFCy+VN5AVhs2+FGeNOLcg5+rvRv3Zh6myBXW9eBs=; b=ramzubN0A1ISmOdpRRzO90b2h/8yevsKGP63amHnTq7pFTPlrfDX3gmNdFuuz74vDf sGe9J4bpR1djEGO/Zwhf5Pv2oN0NlPBffvus00exR0cDlmouKVi7DZ+Itk+KwA3TwjuL wvb2J2CVzsdwlsDm47qGjO79hcWkiWtjHz5F00llzBufBCcSV6I5FObqamK24SYVDjsM /HbAlM3ZlzbhaS4FcCgTiDbu5ML3iImcAR4g8JhgLN34IfZ3ypt7b4RutV3TcS1nBS4b yXJkITEtfK2pmo8cbzyNwXj1GC4gRfBI8pifjqlbd1ydI8NlwFUwNEkhW0JqLjlsAsKK Fukw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=6IYFCy+VN5AVhs2+FGeNOLcg5+rvRv3Zh6myBXW9eBs=; b=TPY/dsL/T0UpFNBtMDZM6nJ1TpGSBjhNFqThY+D9O8kdzecFaaiUpkiZRA2E2hhnYD 6GH9XwhK7yIJraJ3op0uItc5ayL/yhY+DJ6uxgRp8yErEIthHfcPWNiW+jhcFyX254DY LNezqXoF7tbXg4b76s6hlCCpCTyLT6J1oNk6AR245NBAuCE2bC0dBiDyA5vTEJxcesLy F2Jbu1eY3sIUnhQ457ZYJvAZJ5t+Tr0C4JUQPoz+N3FY5PHhtkxyuKKhcKocnJomeSdT hinFSoExb1fjqNl2oYqlcwju8tWeNNp5o6Q3y4Mw12UplPY6gIFiyLWo/iZ8VIKGANMb BDBA== X-Gm-Message-State: AA6/9RnWG62HAhAHP5j1dDg4upZAYvF02sFsdoKm3I8ZuSUHOMWbeDuBFgKWYvYi759uHg== X-Received: by 10.107.15.36 with SMTP id x36mr27810689ioi.114.1474915491174; Mon, 26 Sep 2016 11:44:51 -0700 (PDT) Received: from CABRO3AP00510.localdomain ([74.51.240.241]) by smtp.gmail.com with ESMTPSA id h63sm4330908ita.12.2016.09.26.11.44.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 26 Sep 2016 11:44:50 -0700 (PDT) From: Sylvain Lemieux To: vz@mleia.com, sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH] clk: lpc32xx: fix pwm clock divider computation Date: Mon, 26 Sep 2016 14:44:27 -0400 Message-Id: <1474915467-11101-1-git-send-email-slemieux.tyco@gmail.com> X-Mailer: git-send-email 1.8.3.1 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sylvain Lemieux A zero value in the PWM clock divider register (PWM1_FREQ/PWM2_FREQ) turn off the PWM clock. The "CLK_DIVIDER_ALLOW_ZERO" option is used for hardware that handle the zero divider by not modifying their clock input (i.e. bypass). See "/include/linux/clk-provider.h" for details. Remove the CLK_DIVIDER_ALLOW_ZERO option and add support to handle the clock rate computation of the PWM clock divider 0 value. Signed-off-by: Sylvain Lemieux --- Note: * Should we include a new CLK_DIVIDER option for this case (i.e. clock off when zero ) in "clk-provider.h"? drivers/clk/nxp/clk-lpc32xx.c | 52 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c index 34c9735..3ca3a14 100644 --- a/drivers/clk/nxp/clk-lpc32xx.c +++ b/drivers/clk/nxp/clk-lpc32xx.c @@ -959,6 +959,25 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, divider->flags); } +static unsigned long clk_divider_pwm_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); + unsigned int val; + + regmap_read(clk_regmap, divider->reg, &val); + + val >>= divider->shift; + val &= div_mask(divider->width); + + /* Handle 0 divider -> PWM clock is off. */ + if(val == 0) + return 0; + + return divider_recalc_rate(hw, parent_rate, val, divider->table, + divider->flags); +} + static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { @@ -999,6 +1018,12 @@ static const struct clk_ops lpc32xx_clk_divider_ops = { .set_rate = clk_divider_set_rate, }; +static const struct clk_ops lpc32xx_clk_pwm_divider_ops = { + .recalc_rate = clk_divider_pwm_recalc_rate, + .round_rate = clk_divider_round_rate, + .set_rate = clk_divider_set_rate, +}; + static u8 clk_mux_get_parent(struct clk_hw *hw) { struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw); @@ -1151,6 +1176,25 @@ struct clk_hw_proto { }, \ } +#define LPC32XX_DEFINE_PWM_DIV(_idx, _reg, _shift, _width, _tab, _fl) \ +[CLK_PREFIX(_idx)] = { \ + .type = CLK_DIV, \ + { \ + .hw0 = { \ + .ops = &lpc32xx_clk_pwm_divider_ops, \ + { \ + .div = { \ + .reg = LPC32XX_CLKPWR_ ## _reg, \ + .shift = (_shift), \ + .width = (_width), \ + .table = (_tab), \ + .flags = (_fl), \ + }, \ + }, \ + }, \ + }, \ +} + #define LPC32XX_DEFINE_GATE(_idx, _reg, _bit, _flags) \ [CLK_PREFIX(_idx)] = { \ .type = CLK_GATE, \ @@ -1281,14 +1325,14 @@ static struct clk_hw_proto clk_hw_proto[LPC32XX_CLK_HW_MAX] = { LPC32XX_DEFINE_GATE(MCPWM, TIMCLK_CTRL1, 6, 0), LPC32XX_DEFINE_MUX(PWM1_MUX, PWMCLK_CTRL, 1, 0x1, NULL, 0), - LPC32XX_DEFINE_DIV(PWM1_DIV, PWMCLK_CTRL, 4, 4, NULL, - CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO), + LPC32XX_DEFINE_PWM_DIV(PWM1_DIV, PWMCLK_CTRL, 4, 4, NULL, + CLK_DIVIDER_ONE_BASED), LPC32XX_DEFINE_GATE(PWM1_GATE, PWMCLK_CTRL, 0, 0), LPC32XX_DEFINE_COMPOSITE(PWM1, PWM1_MUX, PWM1_DIV, PWM1_GATE), LPC32XX_DEFINE_MUX(PWM2_MUX, PWMCLK_CTRL, 3, 0x1, NULL, 0), - LPC32XX_DEFINE_DIV(PWM2_DIV, PWMCLK_CTRL, 8, 4, NULL, - CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO), + LPC32XX_DEFINE_PWM_DIV(PWM2_DIV, PWMCLK_CTRL, 8, 4, NULL, + CLK_DIVIDER_ONE_BASED), LPC32XX_DEFINE_GATE(PWM2_GATE, PWMCLK_CTRL, 2, 0), LPC32XX_DEFINE_COMPOSITE(PWM2, PWM2_MUX, PWM2_DIV, PWM2_GATE),