From patchwork Tue Oct 18 00:29:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 9380919 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 95F076086B for ; Tue, 18 Oct 2016 00:29:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8672428FF0 for ; Tue, 18 Oct 2016 00:29:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7B38F28FF3; Tue, 18 Oct 2016 00:29:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 03B4228FF0 for ; Tue, 18 Oct 2016 00:29:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934041AbcJRA33 (ORCPT ); Mon, 17 Oct 2016 20:29:29 -0400 Received: from mail-vk0-f65.google.com ([209.85.213.65]:36788 "EHLO mail-vk0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932779AbcJRA32 (ORCPT ); Mon, 17 Oct 2016 20:29:28 -0400 Received: by mail-vk0-f65.google.com with SMTP id b186so8856128vkb.3 for ; Mon, 17 Oct 2016 17:29:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9/mZKm227WVqJTuy7R/Nkct0FOrVE6cxF8OWLhc+Pjc=; b=C3p0LKU0GucJq5TaNczSBDh+9BL1wsJ2DeW8ja+ZSDsaLcTN5tW+O4XPIEMZYIQxG7 jSE9EyhNaQi7t9jHbkGal/u1cB9IKbD0AnyYsYolYxI0bx+RsI/+nW8s0e9KLd6EtKi9 qdD22YGQnx9dho5GPtcF9pHsUNkYh2Lq4rbhwUTu+m5QzpHb8uamzKw+nCQ2RZyKd8qN BRGD+MtlyzoLLUtMmyjR41B1/0dTA1nhH4xret+M7ZkR7jX7wivQ6LEGkgwkByWTtu3F AWrpvO0fLM7K2KR8KCjrB4d7SiEOCOz48rs9n5RqWH6h21WXFMFL/pXRRkt8+stZ+OBN 5Ejg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9/mZKm227WVqJTuy7R/Nkct0FOrVE6cxF8OWLhc+Pjc=; b=eO7VkKHo1KGLvHwS9S57Fg6Y0j3VD2C+O+sHE9wR3a2/DwcUKhPKu19moRnmByjn57 dq6qPV7vdeEwc0JT5jWjRFmzfsmItTJnbchxW4mEMOq43J8os8NcYYzfosKYc2DOSd+u c9ddV2n+ii4NwWCBuaHsp2BIQBel2FNwUxEGgbOSQ1+/zlVIf2O1N/q/n6Aro6JTSzgw OhwEf+daFG/WFta3k9GJ7vJBMbS5FLTLFxDXj7WPHMesongymzRntNP5Xc6hsZM+QtzP lUrlRHcYh2g0k5Vic72zYH/cak3EYuLHTn25ObeTLSmVoFfiiutKVUHeXarpN/q4dr6g R8Lg== X-Gm-Message-State: AA6/9Rm949z6ZYQTl5RBJrVGb04XJIm8FCxq92HWXULuX/9Db/4M6oViBTbxFQdkIHby3A== X-Received: by 10.31.161.150 with SMTP id k144mr187734vke.12.1476750567929; Mon, 17 Oct 2016 17:29:27 -0700 (PDT) Received: from localhost.localdomain ([2804:14c:482:75c:b07a:d1b9:1470:e9c]) by smtp.gmail.com with ESMTPSA id y76sm6247544vkc.23.2016.10.17.17.29.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Oct 2016 17:29:27 -0700 (PDT) From: Fabio Estevam To: sboyd@codeaurora.org Cc: shawnguo@kernel.org, kernel@pengutronix.de, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Philipp Zabel , Fabio Estevam Subject: [PATCH RESEND 2/3] clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only Date: Mon, 17 Oct 2016 22:29:13 -0200 Message-Id: <1476750554-21961-2-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1476750554-21961-1-git-send-email-festevam@gmail.com> References: <1476750554-21961-1-git-send-email-festevam@gmail.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Philipp Zabel Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. As this can not be guaranteed by the clock framework during runtime, make the ldb_di[x]_sel muxes read-only. A workaround to set the muxes once during boot could be added to the kernel or bootloader. Signed-off-by: Philipp Zabel Signed-off-by: Fabio Estevam --- drivers/clk/imx/clk-imx6q.c | 10 ++-------- drivers/clk/imx/clk.h | 8 ++++++++ 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 66825a8..a4f4de5 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -345,8 +345,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); - clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); - clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); + clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); + clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); @@ -597,12 +597,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); - if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || - clk_on_imx6dl()) { - clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - } - clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000); if (clk_on_imx6dl()) clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 3799ff8..4afad3b 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -75,6 +75,14 @@ static inline struct clk *imx_clk_fixed(const char *name, int rate) return clk_register_fixed_rate(NULL, name, NULL, 0, rate); } +static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, + u8 shift, u8 width, const char **parents, int num_parents) +{ + return clk_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg, + shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock); +} + static inline struct clk *imx_clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div) {