From patchwork Fri Oct 21 03:32:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erin Lo X-Patchwork-Id: 9387989 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C49C260487 for ; Fri, 21 Oct 2016 03:34:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BAB7429DAE for ; Fri, 21 Oct 2016 03:34:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ADC2429DB1; Fri, 21 Oct 2016 03:34:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3E87929DAE for ; Fri, 21 Oct 2016 03:34:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752814AbcJUDdu (ORCPT ); Thu, 20 Oct 2016 23:33:50 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:46962 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752116AbcJUDdI (ORCPT ); Thu, 20 Oct 2016 23:33:08 -0400 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1991268516; Fri, 21 Oct 2016 11:32:52 +0800 Received: from mtkslt209.mediatek.inc (10.21.15.96) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Fri, 21 Oct 2016 11:25:44 +0800 From: Erin Lo To: Matthias Brugger , Mike Turquette , Stephen Boyd , Rob Herring CC: Arnd Bergmann , Sascha Hauer , Daniel Kurtz , Philipp Zabel , , , , , , , , , Shunli Wang , James Liao , Erin Lo Subject: [PATCH v14 2/4] reset: mediatek: Add MT2701 reset driver Date: Fri, 21 Oct 2016 11:32:20 +0800 Message-ID: <1477020742-13889-3-git-send-email-erin.lo@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477020742-13889-1-git-send-email-erin.lo@mediatek.com> References: <1477020742-13889-1-git-send-email-erin.lo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shunli Wang In infrasys and perifsys, there are many reset control bits for kinds of modules. These bits are used as actual reset controllers to be registered into kernel's generic reset controller framework. Signed-off-by: Shunli Wang Signed-off-by: James Liao Signed-off-by: Erin Lo Tested-by: John Crispin Acked-by: Philipp Zabel --- drivers/clk/mediatek/clk-mt2701-hif.c | 6 +++++- drivers/clk/mediatek/clk-mt2701.c | 12 ++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index e2b0039..4c0688f 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -53,8 +53,12 @@ static int mtk_hifsys_init(struct platform_device *pdev) clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + return r; - return r; + mtk_register_reset_controller(node, 1, 0x34); + + return 0; } static const struct of_device_id of_match_clk_mt2701_hif[] = { diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index c225256..b2148b6 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -802,8 +802,12 @@ static int mtk_infrasys_init(struct platform_device *pdev) infra_clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); + if (r) + return r; - return r; + mtk_register_reset_controller(node, 2, 0x30); + + return 0; } static const struct mtk_gate_regs peri0_cg_regs = { @@ -920,8 +924,12 @@ static int mtk_pericfg_init(struct platform_device *pdev) &lock, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + return r; - return r; + mtk_register_reset_controller(node, 2, 0x0); + + return 0; } #define MT8590_PLL_FMAX (2000 * MHZ)