From patchwork Mon Nov 7 13:05:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel FERNANDEZ X-Patchwork-Id: 9415103 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D48CB6022E for ; Mon, 7 Nov 2016 13:10:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C5C8228B6C for ; Mon, 7 Nov 2016 13:10:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B909B28BBE; Mon, 7 Nov 2016 13:10:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6C7DE28B6C for ; Mon, 7 Nov 2016 13:10:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753474AbcKGNJg (ORCPT ); Mon, 7 Nov 2016 08:09:36 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:48255 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753440AbcKGNIv (ORCPT ); Mon, 7 Nov 2016 08:08:51 -0500 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id uA7D4IBu013205; Mon, 7 Nov 2016 14:07:59 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 26h76hgb0j-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 07 Nov 2016 14:07:59 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1549731; Mon, 7 Nov 2016 13:07:59 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 99BFE28F0; Mon, 7 Nov 2016 13:07:58 +0000 (GMT) Received: from localhost (10.48.1.80) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.294.0; Mon, 7 Nov 2016 14:07:58 +0100 From: To: Rob Herring , Mark Rutland , Russell King , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Nicolas Pitre , Arnd Bergmann , , CC: , , , , , , , , Subject: [PATCH 3/6] clk: stm32f4: Add post divisor for I2S & SAI PLLs and Add lcd-tft clock Date: Mon, 7 Nov 2016 14:05:40 +0100 Message-ID: <1478523943-23142-4-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1478523943-23142-1-git-send-email-gabriel.fernandez@st.com> References: <1478523943-23142-1-git-send-email-gabriel.fernandez@st.com> MIME-Version: 1.0 X-Originating-IP: [10.48.1.80] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-11-07_05:, , signatures=0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gabriel Fernandez This patch adds post dividers of I2S & SAI PLLs. These dividers are managed by a dedicated register (RCC_DCKCFGR). The PLL should be off before a set rate. This patch also introduces the lcd-tft clock. Signed-off-by: Gabriel Fernandez --- drivers/clk/clk-stm32f4.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index dda15bc..5fa5d51 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -215,6 +215,7 @@ struct stm32f4_gate_data { enum { SYSTICK, FCLK, CLK_LSI, CLK_LSE, CLK_HSE_RTC, CLK_RTC, PLL_VCO_I2S, PLL_VCO_SAI, + CLK_LCD, END_PRIMARY_CLK }; @@ -599,6 +600,9 @@ static struct clk_hw *clk_register_pll_div(const char *name, static const struct clk_div_table pll_divp_table[] = { { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, }; +static const struct clk_div_table pll_lcd_div_table[] = { + { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 }, +}; /* * Decode current PLL state and (statically) model the state we inherit from @@ -659,16 +663,35 @@ static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc, clk_register_pll_div(data->p_name, data->vco_name, 0, reg, 16, 2, 0, pll_divp_table, pll_hw, lock); - if (data->q_name) + if (data->q_name) { clk_register_pll_div(data->q_name, data->vco_name, 0, reg, 24, 4, CLK_DIVIDER_ONE_BASED, NULL, pll_hw, lock); - if (data->r_name) + if (data->pll_num == PLL_I2S) + clk_register_pll_div("plli2s-q-div", data->q_name, + 0, base + STM32F4_RCC_DCKCFGR, + 0, 5, 0, NULL, pll_hw, &stm32f4_clk_lock); + + if (data->pll_num == PLL_SAI) + clk_register_pll_div("pllsai-q-div", data->q_name, + 0, base + STM32F4_RCC_DCKCFGR, + 8, 5, 0, NULL, pll_hw, &stm32f4_clk_lock); + } + + if (data->r_name) { clk_register_pll_div(data->r_name, data->vco_name, 0, reg, 28, 3, CLK_DIVIDER_ONE_BASED, NULL, pll_hw, lock); + if (data->pll_num == PLL_SAI) + clks[CLK_LCD] = clk_register_pll_div("lcd-tft", + data->r_name, CLK_SET_RATE_PARENT, + base + STM32F4_RCC_DCKCFGR, 16, 2, 0, + pll_lcd_div_table, pll_hw, + &stm32f4_clk_lock); + } + return pll_hw; }