From patchwork Mon Nov 7 13:05:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel FERNANDEZ X-Patchwork-Id: 9415115 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1A8446022E for ; Mon, 7 Nov 2016 13:10:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B6DC28B6C for ; Mon, 7 Nov 2016 13:10:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F13FC28BBE; Mon, 7 Nov 2016 13:10:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6355628B6C for ; Mon, 7 Nov 2016 13:10:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753192AbcKGNKT (ORCPT ); Mon, 7 Nov 2016 08:10:19 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:48248 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753161AbcKGNIu (ORCPT ); Mon, 7 Nov 2016 08:08:50 -0500 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id uA7D4IBv013205; Mon, 7 Nov 2016 14:08:02 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 26h76hgb0t-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 07 Nov 2016 14:08:02 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DBDB234; Mon, 7 Nov 2016 13:08:01 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B3B0828F4; Mon, 7 Nov 2016 13:08:01 +0000 (GMT) Received: from localhost (10.48.1.80) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.294.0; Mon, 7 Nov 2016 14:08:01 +0100 From: To: Rob Herring , Mark Rutland , Russell King , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Nicolas Pitre , Arnd Bergmann , , CC: , , , , , , , , Subject: [PATCH 5/6] clk: stm32f4: Add SAI clocks Date: Mon, 7 Nov 2016 14:05:42 +0100 Message-ID: <1478523943-23142-6-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1478523943-23142-1-git-send-email-gabriel.fernandez@st.com> References: <1478523943-23142-1-git-send-email-gabriel.fernandez@st.com> MIME-Version: 1.0 X-Originating-IP: [10.48.1.80] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-11-07_05:, , signatures=0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gabriel Fernandez This patch introduces SAI clocks for stm32f4 socs. Signed-off-by: Gabriel Fernandez --- drivers/clk/clk-stm32f4.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index b7cb359..c305659 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -217,6 +217,7 @@ enum { PLL_VCO_I2S, PLL_VCO_SAI, CLK_LCD, CLK_I2S, + CLK_SAI1, CLK_SAI2, END_PRIMARY_CLK }; @@ -970,6 +971,9 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name, static const char *i2s_parents[2] = { "plli2s-r", NULL }; +static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL, + "no-clock" }; + struct stm32f4_clk_data { const struct stm32f4_gate_data *gates_data; const u64 *gates_map; @@ -1063,6 +1067,19 @@ static void __init stm32f4_rcc_init(struct device_node *np) i2s_parents, ARRAY_SIZE(i2s_parents), 0, base + STM32F4_RCC_CFGR, 23, 1, 0, NULL, &stm32f4_clk_lock); + + sai_parents[2] = i2s_in_clk; + + clks[CLK_SAI1] = clk_hw_register_mux_table(NULL, "sai1-clk", + sai_parents, ARRAY_SIZE(sai_parents), 0, + base + STM32F4_RCC_DCKCFGR, 20, 1, 0, NULL, + &stm32f4_clk_lock); + + clks[CLK_SAI2] = clk_hw_register_mux_table(NULL, "sai2-clk", + sai_parents, ARRAY_SIZE(sai_parents), 0, + base + STM32F4_RCC_DCKCFGR, 22, 1, 0, NULL, + &stm32f4_clk_lock); + sys_parents[1] = hse_clk; clk_register_mux_table( NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,