From patchwork Mon Nov 14 06:00:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ritesh Harjani X-Patchwork-Id: 9426571 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9A1E260233 for ; Mon, 14 Nov 2016 06:02:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8C256288F4 for ; Mon, 14 Nov 2016 06:02:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 80C18288FA; Mon, 14 Nov 2016 06:02:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0633D288F4 for ; Mon, 14 Nov 2016 06:02:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964900AbcKNGC0 (ORCPT ); Mon, 14 Nov 2016 01:02:26 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:42596 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S941072AbcKNGCY (ORCPT ); Mon, 14 Nov 2016 01:02:24 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6D0FA614FB; Mon, 14 Nov 2016 06:02:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479103343; bh=s/iXEg38EP3XHd8foe9gZc0LD5xrher7rouvYRJeNDA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TQrqRSe6y2pEsVXvc+jvZo5aX/GCn0pp5ERZpdD0s7HBhmFJliB2XLWAwmOIK360M mUF+cMrWS+k4U7QAeW1sAoW80FkUG9gV0YnGkOEJSN/ZwrWNiHthdp86hNatDhZi0l 5KLzIEnBu5rpSubKPwlBg9my1Y5M8CsMZiskb/WA= Received: from rharjani-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: riteshh@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id DFF526151E; Mon, 14 Nov 2016 06:02:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479103340; bh=s/iXEg38EP3XHd8foe9gZc0LD5xrher7rouvYRJeNDA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oopqkMPrTzl86TCk42ane+6i4/Ok0t1Mey8M5xxaBFD8Muytj8n9I3r8Z6V7l0lUI m2SY3KqKdK8/xEIZeFwwce5vDrCsJgG+zuneopx+3EEMTJ9GX8zR44danWeiVnyNnR ISeO11SrDyrgYMDxp4rQBPay099YGdS09v8lc/XI= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org DFF526151E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=riteshh@codeaurora.org From: Ritesh Harjani To: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, shawn.lin@rock-chips.com, sboyd@codeaurora.org, andy.gross@linaro.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, david.brown@linaro.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, alex.lemberg@sandisk.com, mateusz.nowak@intel.com, Yuliy.Izrailov@sandisk.com, asutoshd@codeaurora.org, kdorfman@codeaurora.org, david.griego@linaro.org, stummala@codeaurora.org, venkatg@codeaurora.org, rnayak@codeaurora.org, pramod.gurav@linaro.org, Ritesh Harjani Subject: [PATCH v7 09/14] mmc: sdhci-msm: Add clock changes for DDR mode. Date: Mon, 14 Nov 2016 11:30:43 +0530 Message-Id: <1479103248-9491-10-git-send-email-riteshh@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1479103248-9491-1-git-send-email-riteshh@codeaurora.org> References: <1479103248-9491-1-git-send-email-riteshh@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP SDHC MSM controller need 2x clock for MCLK at GCC. Hence make required changes to have 2x clock for DDR timing modes. Signed-off-by: Ritesh Harjani Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-msm.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index b96a4a7..41a4ea7 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -637,6 +637,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + struct mmc_ios curr_ios = host->mmc->ios; int rc; if (!clock) { @@ -645,11 +646,23 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) } spin_unlock_irq(&host->lock); + /* + * The SDHC requires internal clock frequency to be double the + * actual clock that will be set for DDR mode. The controller + * uses the faster clock(100/400MHz) for some of its parts and + * send the actual required clock (50/200MHz) to the card. + */ + if ((curr_ios.timing == MMC_TIMING_UHS_DDR50) || + (curr_ios.timing == MMC_TIMING_MMC_DDR52) || + (curr_ios.timing == MMC_TIMING_MMC_HS400)) + clock *= 2; + if (clock != msm_host->clk_rate) { rc = clk_set_rate(msm_host->clk, clock); if (rc) { - pr_err("%s: Failed to set clock at rate %u\n", - mmc_hostname(host->mmc), clock); + pr_err("%s: Failed to set clock at rate %u at timing %d\n", + mmc_hostname(host->mmc), clock, + curr_ios.timing); spin_lock_irq(&host->lock); goto out; }