From patchwork Mon Nov 14 06:00:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ritesh Harjani X-Patchwork-Id: 9426547 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5570A60233 for ; Mon, 14 Nov 2016 06:01:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 47177288F4 for ; Mon, 14 Nov 2016 06:01:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3BA43288FA; Mon, 14 Nov 2016 06:01:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9FE7A288F4 for ; Mon, 14 Nov 2016 06:01:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753461AbcKNGBz (ORCPT ); Mon, 14 Nov 2016 01:01:55 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:41546 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752875AbcKNGBx (ORCPT ); Mon, 14 Nov 2016 01:01:53 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 71B2661567; Mon, 14 Nov 2016 06:01:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479103312; bh=eMgILgZ2upfZUEJof9VEZZr5m+BZtkNAeVVwFcJCjik=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SLH91vfD0/dUKrV/H9iDXKRR0/czzXs8OEzbJfaAMFBpCxXdYdhhvmxnuTd3hOQO9 zYqGNWyMTsyGmJ9kqBb8gQ2EMefVz2yffDl3+8FkOytDPFNJgBMxpn3G67MBdgmZ2K CH28AoAZXDjFEfIQI7i33vy5jQ6M1PjyDUecgpY8= Received: from rharjani-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: riteshh@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id C6A8861515; Mon, 14 Nov 2016 06:01:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479103309; bh=eMgILgZ2upfZUEJof9VEZZr5m+BZtkNAeVVwFcJCjik=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SUpkik9ckbzv+Qi0upC9X8qEFRPPWyv++N2N0aSChgl2exJkBwnbcHVFCHhyy6zY+ SL1DV4if/7QfZYAvQzbljLRu8LMSd7E7mUFHKUfNsj/4Zy4hIMc+VF1S2DzhVWRLfr y9r+yNVLhk8XqPG5r/OAY9NiSMyrr9gOG2wYuMoM= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org C6A8861515 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=riteshh@codeaurora.org From: Ritesh Harjani To: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, shawn.lin@rock-chips.com, sboyd@codeaurora.org, andy.gross@linaro.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, david.brown@linaro.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, alex.lemberg@sandisk.com, mateusz.nowak@intel.com, Yuliy.Izrailov@sandisk.com, asutoshd@codeaurora.org, kdorfman@codeaurora.org, david.griego@linaro.org, stummala@codeaurora.org, venkatg@codeaurora.org, rnayak@codeaurora.org, pramod.gurav@linaro.org, Ritesh Harjani Subject: [PATCH v7 05/14] mmc: sdhci-msm: Update DLL reset sequence Date: Mon, 14 Nov 2016 11:30:39 +0530 Message-Id: <1479103248-9491-6-git-send-email-riteshh@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1479103248-9491-1-git-send-email-riteshh@codeaurora.org> References: <1479103248-9491-1-git-send-email-riteshh@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Venkat Gopalakrishnan SDCC core with minor version >= 0x42 introduced new 14lpp DLL. This has additional requirements in the reset sequence for DLL tuning. Make necessary changes as needed. Without this patch we see below errors on such SDHC controllers sdhci_msm 7464900.sdhci: mmc0: DLL failed to LOCK mmc0: tuning execution failed: -110 Signed-off-by: Venkat Gopalakrishnan Signed-off-by: Ritesh Harjani Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-msm.c | 61 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 6ea89c2..643956e 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -58,6 +58,10 @@ #define CORE_DLL_CONFIG 0x100 #define CORE_DLL_STATUS 0x108 +#define CORE_DLL_CONFIG_2 0x1b4 +#define CORE_FLL_CYCLE_CNT BIT(18) +#define CORE_DLL_CLOCK_DISABLE BIT(21) + #define CORE_VENDOR_SPEC 0x10c #define CORE_CLK_PWRSAVE BIT(1) @@ -75,7 +79,9 @@ struct sdhci_msm_host { struct clk *clk; /* main SD/MMC bus clock */ struct clk *pclk; /* SDHC peripheral bus clock */ struct clk *bus_clk; /* SDHC bus voter clock */ + struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/ struct mmc_host *mmc; + bool use_14lpp_dll_reset; }; /* Platform specific tuning */ @@ -304,6 +310,8 @@ static inline void msm_cm_dll_set_freq(struct sdhci_host *host) static int msm_init_cm_dll(struct sdhci_host *host) { struct mmc_host *mmc = host->mmc; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); int wait_cnt = 50; unsigned long flags; u32 config; @@ -319,6 +327,16 @@ static int msm_init_cm_dll(struct sdhci_host *host) config &= ~CORE_CLK_PWRSAVE; writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); + if (msm_host->use_14lpp_dll_reset) { + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); + config &= ~CORE_CK_OUT_EN; + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); + + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); + config |= CORE_DLL_CLOCK_DISABLE; + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); + } + /* Write 1 to DLL_RST bit of DLL_CONFIG register */ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); config |= CORE_DLL_RST; @@ -330,6 +348,28 @@ static int msm_init_cm_dll(struct sdhci_host *host) writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); msm_cm_dll_set_freq(host); + if (msm_host->use_14lpp_dll_reset && + !IS_ERR_OR_NULL(msm_host->xo_clk)) { + u32 mclk_freq = 0; + + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); + config &= CORE_FLL_CYCLE_CNT; + if (config) + mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8), + clk_get_rate(msm_host->xo_clk)); + else + mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4), + clk_get_rate(msm_host->xo_clk)); + + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); + config &= ~(0xFF << 10); + config |= mclk_freq << 10; + + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); + /* wait for 5us before enabling DLL clock */ + udelay(5); + } + /* Write 0 to DLL_RST bit of DLL_CONFIG register */ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); config &= ~CORE_DLL_RST; @@ -340,6 +380,14 @@ static int msm_init_cm_dll(struct sdhci_host *host) config &= ~CORE_DLL_PDN; writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); + if (msm_host->use_14lpp_dll_reset) { + msm_cm_dll_set_freq(host); + /* Enable the DLL clock */ + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); + config &= ~CORE_DLL_CLOCK_DISABLE; + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); + } + /* Set DLL_EN bit to 1. */ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); config |= CORE_DLL_EN; @@ -595,6 +643,16 @@ static int sdhci_msm_probe(struct platform_device *pdev) goto pclk_disable; } + /* + * xo_clock is needed for FLL feature of cm_dll. + * In case if xo_clock is not mentioned in DT, warn and proceed. + */ + msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo_clock"); + if (IS_ERR(msm_host->xo_clk)) { + ret = PTR_ERR(msm_host->xo_clk); + dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret); + } + /* Vote for maximum clock rate for maximum performance */ ret = clk_set_rate(msm_host->clk, INT_MAX); if (ret) @@ -641,6 +699,9 @@ static int sdhci_msm_probe(struct platform_device *pdev) dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", core_version, core_major, core_minor); + if (core_major == 1 && core_minor >= 0x42) + msm_host->use_14lpp_dll_reset = true; + /* * Support for some capabilities is not advertised by newer * controller versions and must be explicitly enabled.