From patchwork Wed Nov 16 16:00:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ritesh Harjani X-Patchwork-Id: 9431999 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3F8F960471 for ; Wed, 16 Nov 2016 16:02:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2E2F128F50 for ; Wed, 16 Nov 2016 16:02:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 226AA28F5E; Wed, 16 Nov 2016 16:02:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3586A28F51 for ; Wed, 16 Nov 2016 16:02:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932162AbcKPQCL (ORCPT ); Wed, 16 Nov 2016 11:02:11 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:46984 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751688AbcKPQCK (ORCPT ); Wed, 16 Nov 2016 11:02:10 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id ADE8B61516; Wed, 16 Nov 2016 16:02:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479312129; bh=xE4cgitbsYJov8U+v3sNkQY1Rn1cYA2y+RwU0KNZ35A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IOmoIcqXRe5xBhQPCiSh1DINmnzwb6Oi3/kGuKeQIKJ9vWIHPR9J1OVd4iF1CxG+2 mN7EWAqnSLsI/nb5rd/tYuFTZCjiDVaFQ6afrGOHzh0OFET7CZy2Md8POHmrGIw0sf qtX5Z30MBUkqlxgTwqDaqHYSEWYKpBRlipxbkGSQ= Received: from rharjani-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: riteshh@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5D5816151E; Wed, 16 Nov 2016 16:01:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479312126; bh=xE4cgitbsYJov8U+v3sNkQY1Rn1cYA2y+RwU0KNZ35A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jqPLvogR/wDA4k92aRT8V7kbLlMm4neUQWReQmjpqi167WOtE237KEku0aRGjqffQ DJnResRjdsar1NhgBg+q3p+/QYMSCf3n7vRhD6SGq1SLLkFn8A0VjBAH++RlZdSef7 a5z/ZumzcrV3vz2HxtdsQ+wKp2Vp6Bgk3ksk0ggw= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 5D5816151E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=riteshh@codeaurora.org From: Ritesh Harjani To: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, sboyd@codeaurora.org, andy.gross@linaro.org Cc: shawn.lin@rock-chips.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, david.brown@linaro.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, alex.lemberg@sandisk.com, mateusz.nowak@intel.com, Yuliy.Izrailov@sandisk.com, asutoshd@codeaurora.org, david.griego@linaro.org, stummala@codeaurora.org, venkatg@codeaurora.org, rnayak@codeaurora.org, pramod.gurav@linaro.org, jeremymc@redhat.com, Ritesh Harjani Subject: [PATCH v8 03/16] mmc: sdhci-msm: Change poor style writel/readl of registers Date: Wed, 16 Nov 2016 21:30:39 +0530 Message-Id: <1479312052-22396-4-git-send-email-riteshh@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1479312052-22396-1-git-send-email-riteshh@codeaurora.org> References: <1479312052-22396-1-git-send-email-riteshh@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch changes the poor style of writel/readl registers into more readable format. This avoid mixed style format of readl/writel in sdhci-msm driver. This patch also removes the one line comments which were present for above writel/readl, since they were of no help. Signed-off-by: Ritesh Harjani Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-msm.c | 62 +++++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 30 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index b78d72f..2dcbeb0 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -138,9 +138,9 @@ static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT; writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); - /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); + config |= CORE_CK_OUT_EN; + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ rc = msm_dll_poll_ck_out_en(host, 1); @@ -307,6 +307,7 @@ static int msm_init_cm_dll(struct sdhci_host *host) struct mmc_host *mmc = host->mmc; int wait_cnt = 50; unsigned long flags; + u32 config; spin_lock_irqsave(&host->lock, flags); @@ -315,33 +316,34 @@ static int msm_init_cm_dll(struct sdhci_host *host) * tuning is in progress. Keeping PWRSAVE ON may * turn off the clock. */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) - & ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC); + config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); + config &= ~CORE_CLK_PWRSAVE; + writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); - /* Write 1 to DLL_RST bit of DLL_CONFIG register */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); + config |= CORE_DLL_RST; + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); - /* Write 1 to DLL_PDN bit of DLL_CONFIG register */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); + config |= CORE_DLL_PDN; + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); msm_cm_dll_set_freq(host); - /* Write 0 to DLL_RST bit of DLL_CONFIG register */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); + config &= ~CORE_DLL_RST; + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); - /* Write 0 to DLL_PDN bit of DLL_CONFIG register */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); + config &= ~CORE_DLL_PDN; + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); - /* Set DLL_EN bit to 1. */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG); + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); + config |= CORE_DLL_EN; + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); - /* Set CK_OUT_EN bit to 1. */ - writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) - | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); + config |= CORE_CK_OUT_EN; + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) & @@ -538,7 +540,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) struct resource *core_memres; int ret; u16 host_version, core_minor; - u32 core_version, caps; + u32 core_version, config; u8 core_major; host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host)); @@ -606,9 +608,9 @@ static int sdhci_msm_probe(struct platform_device *pdev) goto clk_disable; } - /* Reset the core and Enable SDHC mode */ - writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) | - CORE_SW_RST, msm_host->core_mem + CORE_POWER); + config = readl_relaxed(msm_host->core_mem + CORE_POWER); + config |= CORE_SW_RST; + writel_relaxed(config, msm_host->core_mem + CORE_POWER); /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */ usleep_range(1000, 5000); @@ -638,9 +640,9 @@ static int sdhci_msm_probe(struct platform_device *pdev) * controller versions and must be explicitly enabled. */ if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { - caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); - caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; - writel_relaxed(caps, host->ioaddr + + config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); + config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; + writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC_CAPABILITIES0); }