From patchwork Thu Nov 24 14:45:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel FERNANDEZ X-Patchwork-Id: 9445619 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9CA0260235 for ; Thu, 24 Nov 2016 14:49:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9302C27F9F for ; Thu, 24 Nov 2016 14:49:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8766E27FA3; Thu, 24 Nov 2016 14:49:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 591CD27F9F for ; Thu, 24 Nov 2016 14:49:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S941107AbcKXOrg (ORCPT ); Thu, 24 Nov 2016 09:47:36 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:51248 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S941115AbcKXOrd (ORCPT ); Thu, 24 Nov 2016 09:47:33 -0500 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id uAOEiWOh031910; Thu, 24 Nov 2016 15:46:34 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 26tegj47nt-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 24 Nov 2016 15:46:34 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9EE2334; Thu, 24 Nov 2016 14:46:33 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 734F12C2F; Thu, 24 Nov 2016 14:46:33 +0000 (GMT) Received: from localhost (10.48.1.80) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.294.0; Thu, 24 Nov 2016 15:46:33 +0100 From: To: Rob Herring , Mark Rutland , Russell King , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Nicolas Pitre , Arnd Bergmann , , , CC: , , , , , , , , Subject: [PATCH v2 6/9] clk: stm32f4: Add SAI clocks Date: Thu, 24 Nov 2016 15:45:46 +0100 Message-ID: <1479998749-20358-7-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479998749-20358-1-git-send-email-gabriel.fernandez@st.com> References: <1479998749-20358-1-git-send-email-gabriel.fernandez@st.com> MIME-Version: 1.0 X-Originating-IP: [10.48.1.80] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-11-24_04:, , signatures=0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gabriel Fernandez This patch introduces SAI clocks for stm32f4 socs. Signed-off-by: Gabriel Fernandez --- Documentation/devicetree/bindings/clock/st,stm32-rcc.txt | 2 ++ drivers/clk/clk-stm32f4.c | 16 ++++++++++++++++ include/dt-bindings/clock/stm32f4-clock.h | 4 +++- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt index 8c1ca68..8f93740 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt @@ -79,6 +79,8 @@ The secondary index is bound with the following magic numbers: 7 PLL_VCO_SAI (vco frequency of SAI pll) 8 CLK_LCD (LCD-TFT) 9 CLK_I2S (I2S clocks) + 10 CLK_SAI1 (audio clocks) + 11 CLK_SAI2 Example: diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 3063b30..02339d1 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -937,6 +937,9 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name, static const char *i2s_parents[2] = { "plli2s-r", NULL }; +static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL, + "no-clock" }; + struct stm32_aux_clk { int idx; const char *name; @@ -977,6 +980,18 @@ struct stm32f4_clk_data { NO_GATE, 0, CLK_SET_RATE_PARENT }, + { + CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents), + STM32F4_RCC_DCKCFGR, 20, 3, + STM32F4_RCC_APB2ENR, 22, + CLK_SET_RATE_PARENT + }, + { + CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents), + STM32F4_RCC_DCKCFGR, 22, 3, + STM32F4_RCC_APB2ENR, 22, + CLK_SET_RATE_PARENT + }, }; static const struct stm32f4_clk_data stm32f429_clk_data = { @@ -1109,6 +1124,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) i2s_in_clk = of_clk_get_parent_name(np, 1); i2s_parents[1] = i2s_in_clk; + sai_parents[2] = i2s_in_clk; clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0, 16000000, 160000); diff --git a/include/dt-bindings/clock/stm32f4-clock.h b/include/dt-bindings/clock/stm32f4-clock.h index b129ab9..5431f00 100644 --- a/include/dt-bindings/clock/stm32f4-clock.h +++ b/include/dt-bindings/clock/stm32f4-clock.h @@ -29,7 +29,9 @@ #define PLL_VCO_SAI 7 #define CLK_LCD 8 #define CLK_I2S 9 +#define CLK_SAI1 10 +#define CLK_SAI2 11 -#define END_PRIMARY_CLK 10 +#define END_PRIMARY_CLK 12 #endif