From patchwork Thu Dec 1 15:27:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel FERNANDEZ X-Patchwork-Id: 9456395 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4908560235 for ; Thu, 1 Dec 2016 15:30:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3C192284F7 for ; Thu, 1 Dec 2016 15:30:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 30D73284F9; Thu, 1 Dec 2016 15:30:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DABD5284F7 for ; Thu, 1 Dec 2016 15:30:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759848AbcLAP24 (ORCPT ); Thu, 1 Dec 2016 10:28:56 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:54319 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1759728AbcLAP2y (ORCPT ); Thu, 1 Dec 2016 10:28:54 -0500 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id uB1FP9PJ017422; Thu, 1 Dec 2016 16:28:05 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 272m4p11vy-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 01 Dec 2016 16:28:05 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4A6FE31; Thu, 1 Dec 2016 15:28:04 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 203392BFE; Thu, 1 Dec 2016 15:28:04 +0000 (GMT) Received: from localhost (10.48.1.80) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.294.0; Thu, 1 Dec 2016 16:28:03 +0100 From: To: Rob Herring , Mark Rutland , Russell King , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Nicolas Pitre , Arnd Bergmann , , , CC: , , , , , , , , Subject: [PATCH v3 3/9] clk: stm32f4: Add post divisor for I2S & SAI PLLs Date: Thu, 1 Dec 2016 16:27:43 +0100 Message-ID: <1480606069-5178-4-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480606069-5178-1-git-send-email-gabriel.fernandez@st.com> References: <1480606069-5178-1-git-send-email-gabriel.fernandez@st.com> MIME-Version: 1.0 X-Originating-IP: [10.48.1.80] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-12-01_12:, , signatures=0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gabriel Fernandez This patch adds post dividers of I2S & SAI PLLs. These dividers are managed by a dedicated register (RCC_DCKCFGR). The PLL should be off before a set rate. Signed-off-by: Gabriel Fernandez --- drivers/clk/clk-stm32f4.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index c2b62cc..98856ac 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -47,6 +47,7 @@ #define STM32F4_RCC_CSR 0x74 #define STM32F4_RCC_PLLI2SCFGR 0x84 #define STM32F4_RCC_PLLSAICFGR 0x88 +#define STM32F4_RCC_DCKCFGR 0x8c struct stm32f4_gate_data { u8 offset; @@ -357,6 +358,18 @@ struct stm32f4_pll { #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate) +struct stm32f4_pll_post_div_data { + u8 pll_num; + const char *name; + const char *parent; + u8 flag; + u8 offset; + u8 shift; + u8 width; + u8 flag_div; + const struct clk_div_table *div_table; +}; + struct stm32f4_vco_data { const char *vco_name; u8 offset; @@ -370,6 +383,18 @@ struct stm32f4_vco_data { { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 }, }; +#define MAX_POST_DIV 3 +static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = { + { PLL_I2S, "plli2s-q-div", "plli2s-q", CLK_SET_RATE_PARENT, + STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL}, + + { PLL_SAI, "pllsai-q-div", "pllsai-q", CLK_SET_RATE_PARENT, + STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL }, + + { PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, + STM32F4_RCC_DCKCFGR, 16, 2, CLK_DIVIDER_POWER_OF_TWO}, +}; + struct stm32f4_div_data { u8 shift; u8 width; @@ -996,6 +1021,23 @@ static void __init stm32f4_rcc_init(struct device_node *np) clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in", &data->pll_data[2], &stm32f4_clk_lock); + for (n = 0; n < MAX_POST_DIV; n++) { + const struct stm32f4_pll_post_div_data *post_div; + + post_div = &post_div_data[n]; + + clk_register_pll_div(post_div->name, + post_div->parent, + post_div->flag, + base + post_div->offset, + post_div->shift, + post_div->width, + post_div->flag_div, + post_div->div_table, + clks[post_div->pll_num], + &stm32f4_clk_lock); + } + sys_parents[1] = hse_clk; clk_register_mux_table( NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,