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Thu, 22 Dec 2016 09:44:41 +0000 (GMT) X-AuditID: b6c32a58-f79726d000001ac1-3b-585ba08968cc Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 0A.D0.28332.980AB585; Thu, 22 Dec 2016 18:44:41 +0900 (KST) Received: from AMDC2765.digital.local ([106.116.147.25]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OIK00MB2Z281V20@mmp1.samsung.com>; Thu, 22 Dec 2016 18:44:41 +0900 (KST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi Subject: [PATCH] clk/samsung: exynos542x: mark some clocks as critical Date: Thu, 22 Dec 2016 10:44:30 +0100 Message-id: <1482399870-18563-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrKIsWRmVeSWpSXmKPExsWy7bCmlm7ngugIg5lnLCw2zljPanH9y3NW i/PnN7BbfOy5x2ox4/w+Jou1R+6yWxx+087qwO6xaVUnm0ffllWMHp83yQUwR3HZpKTmZJal FunbJXBlrDo+i71gp1RF243LrA2Mi8S6GDk5JARMJPZcmcMGYYtJXLi3Hsjm4hASWMoocX73 PBYIp51J4u3DoywwHXfmn4FKLGeU+PlsOhOE84tR4s3m58wgVWwChhJdb7vA5ooIOEh8/vSa EaSIWeApo8S9xS1MIAlhATeJe/2HWEFsFgFVibnXD4Ot4BXwkOi718oKsU5O4uSxyawgzRIC Z9gkzhxYCORwADmyEpsOMEPUuEjs633PBGELS7w6voUdwpaW+Lv0FiOE3c8o0dSqDWHPYJQ4 95YXwraWOHz8ItguZgE+id7fT5ggxvNKdLQJQZR4SDy5fgsaRo4S289fACsXEoiVODTpJ/ME RukFjAyrGMVSC4pz01OLTQtM9IoTc4tL89L1kvNzNzGCI1MrYgfjvxlBhxgFOBiVeHgdSqMj hFgTy4orcw8xSnAwK4nwKs4DCvGmJFZWpRblxxeV5qQWH2KU5mBREuddUGEdISSQnliSmp2a WpBaBJNl4uCUamB0uxnycpqrT/uWv1nZzmeYEr//iNut/iOk4s+E4judTdPXhJ/yfPKl+g+/ X9+1dRcmpXyZoRfj7yF7cbvcvOki3IpO5jY/Ow6+mdig3ig6z7l2uZKKvd1bTzkhR1dzvm8H /nP1L/ro7FWkqvvh1/Xc+rB2x/tLBa91We6StlzbaPxjdmmYaqYSS3FGoqEWc1FxIgBQQTyg yAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNLMWRmVeSWpSXmKPExsVy+t9jAd3OBdERBrMOy1tsnLGe1eL6l+es FufPb2C3+Nhzj9Vixvl9TBZrj9xltzj8pp3Vgd1j06pONo++LasYPT5vkgtgjnKzyUhNTEkt UkjNS85PycxLt1UKDXHTtVBSyEvMTbVVitD1DQlSUihLzCkF8owM0ICDc4B7sJK+XYJbxqrj s9gLdkpVtN24zNrAuEisi5GTQ0LAROLO/DMsELaYxIV769m6GLk4hASWMkos6ehiBUkICfxi lFh9wgzEZhMwlOh628UGYosIOEh8/vSaEaSBWeA5o8T73f1gk4QF3CTu9R8Ca2YRUJWYe/0w WJxXwEOi714rK8Q2OYmTxyazTmDkXsDIsIpRIrUguaA4KT3XKC+1XK84Mbe4NC9dLzk/dxMj OCCfSe9gPLzL/RCjAAejEg/vCe7oCCHWxLLiytxDjBIczEoivIrzgEK8KYmVValF+fFFpTmp xYcYTYEOmMgsJZqcD4yWvJJ4QxNzE3NjAwtzS0sTIyVx3sbZz8KFBNITS1KzU1MLUotg+pg4 OKUaGGP+GH+r28Jh9uC7vcf9Cbkr8g6cy/Q4vKi+qjhht3qU/+2cRadM8mp2fNNYurk5XedI s2u5srISy6m+pA4/49UxG0s2vFjMWvqWb8Z8t4YuoV9bxadNZVyyMjZ+32/Dgv5INRW7o6XG RsUcEu8enQvoPHxxx4S0lVHJanv2nZ7yY+GiJTd2XlJiKc5INNRiLipOBACiTLqJXgIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20161222094441epcas5p330bb16763e02149a275c30eb644b0e7c X-Msg-Generator: CA X-Sender-IP: 203.254.230.27 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 105P X-HopCount: 7 X-CMS-RootMailID: 20161222094441epcas5p330bb16763e02149a275c30eb644b0e7c X-RootMTR: 20161222094441epcas5p330bb16763e02149a275c30eb644b0e7c References: Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some parent clocks of the Exynos542x clock blocks, which have separate power domains (like DISP, MFC, MSC, GSC, FSYS and G2D) must be always enabled to access any register related to power management unit or devices connected to it. For the time being, until a proper solution based on runtime PM is applied, mark those clocks as critical (instead of ignore unused or even no flags) to prevent disabling them. Signed-off-by: Marek Szyprowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Reviewed-by: Chanwoo Choi Acked-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5420.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 8c8b495cbf0d..cdc092a1d9ef 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -586,7 +586,7 @@ static void __init exynos5420_clk_sleep_init(void) {} GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", GATE_BUS_TOP, 24, 0, 0), GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", - GATE_BUS_TOP, 27, 0, 0), + GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), }; static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { @@ -956,20 +956,20 @@ static void __init exynos5420_clk_sleep_init(void) {} GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", - GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), + GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0), GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", - GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), + GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0), GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", GATE_BUS_TOP, 5, 0, 0), GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", - GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), + GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", @@ -983,20 +983,20 @@ static void __init exynos5420_clk_sleep_init(void) {} GATE(0, "aclk166", "mout_user_aclk166", GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", - GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), + GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), GATE(0, "aclk400_isp", "mout_user_aclk400_isp", GATE_BUS_TOP, 16, 0, 0), GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", GATE_BUS_TOP, 17, 0, 0), GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", - GATE_BUS_TOP, 18, 0, 0), + GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", GATE_BUS_TOP, 28, 0, 0), GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", GATE_BUS_TOP, 29, 0, 0), GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", - SRC_MASK_TOP2, 24, 0, 0), + SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", SRC_MASK_TOP7, 20, 0, 0),