From patchwork Thu Dec 29 13:36:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartlomiej Zolnierkiewicz X-Patchwork-Id: 9491217 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A768560838 for ; Thu, 29 Dec 2016 13:38:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9D28A1FF15 for ; Thu, 29 Dec 2016 13:38:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 912DF25E13; Thu, 29 Dec 2016 13:38:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 017541FF15 for ; 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Thu, 29 Dec 2016 13:37:28 +0000 (GMT) X-AuditID: b6c32a2c-f79ad6d000007a0b-0a-5865119958b8 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 09.DB.28332.89115685; Thu, 29 Dec 2016 22:37:28 +0900 (KST) Received: from AMDC3058.DIGITAL.local ([106.120.53.102]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OIY00AMG8HZWM40@mmp2.samsung.com>; Thu, 29 Dec 2016 22:37:28 +0900 (KST) From: Bartlomiej Zolnierkiewicz To: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Kukjin Kim , Kukjin Kim , Krzysztof Kozlowski , Javier Martinez Canillas Cc: Doug Anderson , Andreas Faerber , Thomas Abraham , Tobias Jakobi , Ben Gamari , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, b.zolnierkie@samsung.com Subject: [PATCH 1/2] clk: samsung: exynos4412: add cpu clock configuration data for Exynos4412 Prime Date: Thu, 29 Dec 2016 14:36:50 +0100 Message-id: <1483018611-27998-2-git-send-email-b.zolnierkie@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1483018611-27998-1-git-send-email-b.zolnierkie@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAAz1Sa0hTYRjuOzs3zdVpin5oJQz6kaQpJHykSNKFExXUj0KKrJEntZzKjoam 1cjyllPLTPMepOWx0ObyVt5mODJtLtNMcxCaxjJTLLTUyO3M/j3P+z0XvpeXlsiqCXc6MjqO U0UrouSkI97QtX279/1NXIjv9Cd/lKLl0bPCWgIVlY/h6MPPKQL1VXWSaPr7EwxpKgZJlDP+ TYKMxjoKaceHCDSXZSbQQEsJieY1rwAqNLZhyNSzH3VNpxFosfcWjtKrAEqtmSWQ0LIM9riw P4ZvUmyx2oSzA9kajG0uGqNYrZBBsvUPr7F/uylWl7M6ydYJgO1d2svWv0li57VbjzqddAwM 46IiL3GqnUFnHSPu6/qx2EFpQlE/UgPD+kzgQENmFywbFSQidoX95loyEzjSMqYSQP0HNRBJ Gga1I7/wNUdBX51dVQLgVMtzXCR/AByeLCWtKpLZDW+nCTa7CzOPQWNmuY1ImDQJnJjpXG2k aWfmPPz6XW414Mw2+Ll2nLBiKcPCp8ud9rqt8HV3nm3uwByEvQvLlDUHMisUXHw+SFlzILMF ajvsn9gH80ub7F5naDHoKBF7wJXKESDiAgAbl6CYUw+g8CLXLgqAXQaTrUzCbICapQlMzJfC 9FSZKGHhvaF3mIiDoaVqlvq/Cl35EJ4LNleAdQJw5WJ5ZTjH+8f6+fAKJR8fHe5zLkapBbYD 8trRBMwVh/SAoYHcSfr4S1iIjFBc4hOVegBpidxF6r2RC5FJwxSJlzlVzBlVfBTH64EHjcvd pBUJASEyJlwRx13kuFhOtfaK0Q7uahDanvUyfOYQu+2Oc/zXmnzygtu51sLm4APmVJnFJe7t iY7opBuGY57vK72GHa6O3h4LncysG/GdKSv73ZvzMayludrQHuRZfCrCq7SnM6VRVu19b+GB +W5wQ0GkJ2985J+nbEu2mNTrsmIS3a+4m04nJx/WH59YcgvM6Lh+RHBunZPjfITCz0ui4hX/ AMBcUq88AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFIsWRmVeSWpSXmKPExsVy+t9jQd0ZgqkRBpOPqlg0byq22DhjPavF rPl3WSyuf3nOanF22UE2izdv1zBZ9C64ymbR//g1s8X58xvYLTY9vsZq8bHnHqvF5V1z2Cw+ 9x5htJhxfh+TxcVTrhaH37SzWvw4081i0bGM0aJt9QdWi1W7/jA6iHi8v9HK7jG74SKLx+W+ XiaPnbPusntsWtXJ5rF5Sb3Hv2PsHlv6gSJ9W1Yxepz57eyx+XS1x+dNcgE8UW42GamJKalF Cql5yfkpmXnptkqhIW66FkoKeYm5qbZKEbq+IUFKCmWJOaVAnpEBGnBwDnAPVtK3S3DLmLnl AlPBVd6KWRcsGhiPc3cxcnJICJhITD+7gQ3CFpO4cG89mC0kMItRYsF29i5GLiD7F6PE7cXz GUESbAJWEhPbVzGCJEQEPjNJvDn/mw3EYRboZJa42TqJBaRKWCBN4vnnC6wgNouAqsTD9Y/B bF4BD4m1fw6yQKyTkzh5bDJYnFPAU+LM9z/sEKs9JF6c3s42gZF3ASPDKkaJ1ILkguKk9Fyj vNRyveLE3OLSvHS95PzcTYzgeHwmvYPx8C73Q4wCHIxKPLwnFFIihFgTy4orcw8xSnAwK4nw 6vKnRgjxpiRWVqUW5ccXleakFh9iNAU6bCKzlGhyPjBV5JXEG5qYm5gbG1iYW1qaGCmJ8zbO fhYuJJCeWJKanZpakFoE08fEwSnVwGjyTvDtJzO2kvUbGE9ELCw9Hikq6bPjCGeR05VlDbM7 cq2W7mlIPNn5UvzS9b2Hrt9dteTjXfty7oyGVpncWRw1lxi69K+ey5jtXvnjp++rhdNnyD1f sbOpMULPzULYJun6r5i/27SShLl+n/c+7m1ksOdbB9sXL6MXW1v9Ms1ld5fn3Ur29FdiKc5I NNRiLipOBAAHSjY73QIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20161229133728epcas5p1e7d700c4404684f9574e2251d836061c X-Msg-Generator: CA X-Sender-IP: 203.254.230.27 X-Local-Sender: =?UTF-8?B?QmFydGxvbWllaiBab2xuaWVya2lld2ljehtTUlBPTC1LZXJu?= =?UTF-8?B?ZWwgKFRQKRvsgrzshLHsoITsnpAbU2VuaW9yIFNvZnR3YXJlIEVuZ2luZWVy?= X-Global-Sender: =?UTF-8?B?QmFydGxvbWllaiBab2xuaWVya2lld2ljehtTUlBPTC1LZXJu?= =?UTF-8?B?ZWwgKFRQKRtTYW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBF?= =?UTF-8?B?bmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 105P X-HopCount: 7 X-CMS-RootMailID: 20161229133728epcas5p1e7d700c4404684f9574e2251d836061c X-RootMTR: 20161229133728epcas5p1e7d700c4404684f9574e2251d836061c References: <1483018611-27998-1-git-send-email-b.zolnierkie@samsung.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add cpu clock configuration data for Exynos4412 Prime SoC (it supports additional PLL rates & CPU frequencies). Based on Hardkernel's kernel for ODROID-X2/U2/U3 boards. Cc: Doug Anderson Cc: Andreas Faerber Cc: Thomas Abraham Cc: Tobias Jakobi Cc: Ben Gamari Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/clk/samsung/clk-exynos4.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index faab9b3..e40b775 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1298,6 +1298,8 @@ static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx) }; static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = { + PLL_35XX_RATE(1704000000, 213, 3, 0), + PLL_35XX_RATE(1600000000, 200, 3, 0), PLL_35XX_RATE(1500000000, 250, 4, 0), PLL_35XX_RATE(1400000000, 175, 3, 0), PLL_35XX_RATE(1300000000, 325, 6, 0), @@ -1421,6 +1423,8 @@ static void __init exynos4x12_core_down_clock(void) (((cores) << 8) | ((hpm) << 4) | ((copy) << 0)) static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { + { 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), }, + { 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), }, { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },