From patchwork Thu Mar 2 13:22:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 9600935 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8827A60429 for ; Thu, 2 Mar 2017 16:49:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7B42426E97 for ; Thu, 2 Mar 2017 16:49:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6FF0F27CAF; Thu, 2 Mar 2017 16:49:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 41BA82832B for ; Thu, 2 Mar 2017 16:49:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754000AbdCBQs3 (ORCPT ); Thu, 2 Mar 2017 11:48:29 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19279 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753898AbdCBQsW (ORCPT ); Thu, 2 Mar 2017 11:48:22 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 02 Mar 2017 05:22:22 -0800 Received: from HQMAIL104.nvidia.com ([172.20.13.39]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 02 Mar 2017 05:20:34 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 02 Mar 2017 05:20:34 -0800 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Thu, 2 Mar 2017 13:22:15 +0000 Received: from tbergstrom-lnx.Nvidia.com (10.21.24.170) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Thu, 2 Mar 2017 13:22:11 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id 14D8CF8005C; Thu, 2 Mar 2017 15:22:07 +0200 (EET) From: Peter De Schrijver To: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , "Stephen Boyd" , Stephen Warren , "Thierry Reding" , Alexandre Courbot , , , Subject: [PATCH] clk: tegra: fix disable unused for clocks sharing enable bit Date: Thu, 2 Mar 2017 15:22:05 +0200 Message-ID: <1488460925-16793-1-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: DRUKMAIL102.nvidia.com (10.25.59.20) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In case 2 clocks share an enable bit and one of them is enabled by a driver and the other one is not, CCF will think it's enabled because it will only look at the hw state. Therefor it will disable the clock and thus also disable the other clock which was enabled. Solve this by reading the initial state of the enable bit and incrementing the refcount if it's set. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-periph-gate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index 8812782..303ef32 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -159,6 +159,9 @@ struct clk *tegra_clk_register_periph_gate(const char *name, gate->enable_refcnt = enable_refcnt; gate->regs = pregs; + if (read_enb(gate) & periph_clk_to_bit(gate)) + enable_refcnt[clk_num]++; + /* Data in .init is copied by clk_register(), so stack variable OK */ gate->hw.init = &init;