From patchwork Thu Mar 9 12:53:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 9613279 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9E855602B4 for ; Thu, 9 Mar 2017 12:54:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9E9D8285C1 for ; Thu, 9 Mar 2017 12:54:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 938092861E; Thu, 9 Mar 2017 12:54:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 27690285C1 for ; Thu, 9 Mar 2017 12:54:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753678AbdCIMyz (ORCPT ); Thu, 9 Mar 2017 07:54:55 -0500 Received: from mail-wm0-f53.google.com ([74.125.82.53]:35460 "EHLO mail-wm0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754086AbdCIMx6 (ORCPT ); Thu, 9 Mar 2017 07:53:58 -0500 Received: by mail-wm0-f53.google.com with SMTP id v186so138563936wmd.0 for ; Thu, 09 Mar 2017 04:53:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3EFiDQeyEdFOJGfLtsgJUlabjnQqb9t9CopAxrk3+aQ=; b=nNlrUx64F46AWqPZivF0OR5cDQO0sQUqfyyHRpcpV10y+rvpCbaAcKkPDCIXn9bvpx dWdAFRX23fDwNN1VK4ozEjJZvRIFf1sn2VL6CdinWfSdeQwnRXNfFpnOJ7erxU2ysWr3 FrguA+/lbTTQ7d4Z/IXs8v31gqedrGc2AGxPExi5BaZqSz+Ks+q0qcEjmiiYTvbJSc+u I2kPLrLDpZC48JaO+Wk2DoLhw8hq/DQMtQq9I6dEXi8czZUfgQUqv6//m0mOpcnVy/UZ 8rI0ZXz08r770F8px4OF197qlOe7BzG5mRE8pb7fUikTUtgX9cJ2pxIXvAI7BRLau+T/ CviA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3EFiDQeyEdFOJGfLtsgJUlabjnQqb9t9CopAxrk3+aQ=; b=KyI/+8Gw71j07SKA3rrSo9iMROKVkSkKgMuoDgujRApQfY6H+QvixdPc/GbHY1TL3w DrjhFckG1je2iG6bBtfGfgmIwsMszuFXhJ6lHlO50A7mOhXSp3uTMJAlCbtzcxJoho2x vMD828hIfI+NePL34KUrwT4yXaM5h+Wp4FTi+acruLVPYRzoKOEF4IA3k82XCR+37FGl KpycoEbSkl40Fhx7bv5usP4n+UPoWJrf8kw1UNI7o+4hPZHiBNeMIEtVVTNZc/N9yYUd E0VxR5ayrXCl9dK2Tf5hKSkzYH1iKpBHfLxaA1IxbFF3Ep/cRwtxZA7rCG8ypzXi1r1x 6FkA== X-Gm-Message-State: AMke39mG/EEq77nOre5lTA57zy8h7dWX7WP4SkOy+nyETBE0oCVzjFZJYndtq9UbknOfm3c0 X-Received: by 10.28.173.193 with SMTP id w184mr10839639wme.106.1489064035948; Thu, 09 Mar 2017 04:53:55 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id x193sm8695777wme.23.2017.03.09.04.53.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Mar 2017 04:53:55 -0800 (PST) From: Neil Armstrong To: sboyd@codeaurora.org, khilman@baylibre.com, carlo@caione.org Cc: Neil Armstrong , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/3] clk: meson-gxbb: Add MALI clocks Date: Thu, 9 Mar 2017 13:53:46 +0100 Message-Id: <1489064027-18004-3-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1489064027-18004-1-git-send-email-narmstrong@baylibre.com> References: <1489064027-18004-1-git-send-email-narmstrong@baylibre.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Mali is clocked by two identical clock paths behind a glitch free mux to safely change frequency while running. The two "mali_0" and "mali_1" clocks are composed of a mux, divider and gate. Expose these two clocks trees using generic clocks. Finally the glitch free mux is added as "mali" clock. Signed-off-by: Neil Armstrong --- drivers/clk/meson/gxbb.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 139 insertions(+) diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 5059c7b..d9f7fef 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -634,6 +634,131 @@ }, }; +/* + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) + * muxed by a glitch-free switch. + */ + +static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7}; +static const char *gxbb_mali_0_1_parent_names[] = { + "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", + "fclk_div4", "fclk_div3", "fclk_div5" +}; + +static struct clk_mux gxbb_mali_0_sel = { + .reg = (void *)HHI_MALI_CLK_CNTL, + .mask = 0x7, + .shift = 9, + .table = mux_table_mali_0_1, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mali_0_sel", + .ops = &clk_mux_ops, + /* + * bits 10:9 selects from 8 possible parents: + * xtal, gp0_pll, mpll2, mpll1, fclk_div7, + * fclk_div4, fclk_div3, fclk_div5 + */ + .parent_names = gxbb_mali_0_1_parent_names, + .num_parents = 8, + .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_divider gxbb_mali_0_div = { + .reg = (void *)HHI_MALI_CLK_CNTL, + .shift = 0, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mali_0_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "mali_0_sel" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_gate gxbb_mali_0 = { + .reg = (void *)HHI_MALI_CLK_CNTL, + .bit_idx = 8, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mali_0", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "mali_0_div" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_mux gxbb_mali_1_sel = { + .reg = (void *)HHI_MALI_CLK_CNTL, + .mask = 0x7, + .shift = 25, + .table = mux_table_mali_0_1, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mali_1_sel", + .ops = &clk_mux_ops, + /* + * bits 10:9 selects from 8 possible parents: + * xtal, gp0_pll, mpll2, mpll1, fclk_div7, + * fclk_div4, fclk_div3, fclk_div5 + */ + .parent_names = gxbb_mali_0_1_parent_names, + .num_parents = 8, + .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_divider gxbb_mali_1_div = { + .reg = (void *)HHI_MALI_CLK_CNTL, + .shift = 16, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mali_1_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "mali_1_sel" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_gate gxbb_mali_1 = { + .reg = (void *)HHI_MALI_CLK_CNTL, + .bit_idx = 24, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mali_1", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "mali_1_div" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + }, +}; + +static u32 mux_table_mali[] = {0, 1}; +static const char *gxbb_mali_parent_names[] = { + "mali_0", "mali_1" +}; + +static struct clk_mux gxbb_mali = { + .reg = (void *)HHI_MALI_CLK_CNTL, + .mask = 1, + .shift = 31, + .table = mux_table_mali, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mali", + .ops = &clk_mux_ops, + .parent_names = gxbb_mali_parent_names, + .num_parents = 2, + .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), + }, +}; + /* Everything Else (EE) domain gates */ static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); @@ -827,6 +952,13 @@ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, + [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, + [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, + [CLKID_MALI_0] = &gxbb_mali_0.hw, + [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, + [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, + [CLKID_MALI_1] = &gxbb_mali_1.hw, + [CLKID_MALI] = &gxbb_mali.hw, }, .num = NR_CLKS, }; @@ -930,16 +1062,23 @@ &gxbb_emmc_b, &gxbb_emmc_c, &gxbb_sar_adc_clk, + &gxbb_mali_0, + &gxbb_mali_1, }; static struct clk_mux *const gxbb_clk_muxes[] = { &gxbb_mpeg_clk_sel, &gxbb_sar_adc_clk_sel, + &gxbb_mali_0_sel, + &gxbb_mali_1_sel, + &gxbb_mali, }; static struct clk_divider *const gxbb_clk_dividers[] = { &gxbb_mpeg_clk_div, &gxbb_sar_adc_clk_div, + &gxbb_mali_0_div, + &gxbb_mali_1_div, }; static int gxbb_clkc_probe(struct platform_device *pdev)