| Message ID | 1489587055-23722-1-git-send-email-pdeschrijver@nvidia.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Stephen Boyd |
| Headers | show |
On Wed, Mar 15, 2017 at 04:10:54PM +0200, Peter De Schrijver wrote: > In case 2 clocks share an enable bit and one of them is enabled by a driver > and the other one is not, CCF will think it's enabled because it will only > look at the hw state. Therefor it will disable the clock and thus also > disable the other clock which was enabled. Solve this by reading the > initial state of the enable bit and incrementing the refcount if it's set. > > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> > --- > drivers/clk/tegra/clk-periph-gate.c | 3 +++ > 1 file changed, 3 insertions(+) I think you had already sent a version of this patch a couple of weeks ago. I've applied the first version since I couldn't spot any delta between them. Thierry
On Mon, Mar 20, 2017 at 02:27:46PM +0100, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Wed, Mar 15, 2017 at 04:10:54PM +0200, Peter De Schrijver wrote: > > In case 2 clocks share an enable bit and one of them is enabled by a driver > > and the other one is not, CCF will think it's enabled because it will only > > look at the hw state. Therefor it will disable the clock and thus also > > disable the other clock which was enabled. Solve this by reading the > > initial state of the enable bit and incrementing the refcount if it's set. > > > > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> > > --- > > drivers/clk/tegra/clk-periph-gate.c | 3 +++ > > 1 file changed, 3 insertions(+) > > I think you had already sent a version of this patch a couple of weeks > ago. I've applied the first version since I couldn't spot any delta > between them. Hmm. Could be. Cheers, Peter. -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index 8812782..303ef32 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -159,6 +159,9 @@ struct clk *tegra_clk_register_periph_gate(const char *name, gate->enable_refcnt = enable_refcnt; gate->regs = pregs; + if (read_enb(gate) & periph_clk_to_bit(gate)) + enable_refcnt[clk_num]++; + /* Data in .init is copied by clk_register(), so stack variable OK */ gate->hw.init = &init;
In case 2 clocks share an enable bit and one of them is enabled by a driver and the other one is not, CCF will think it's enabled because it will only look at the hw state. Therefor it will disable the clock and thus also disable the other clock which was enabled. Solve this by reading the initial state of the enable bit and incrementing the refcount if it's set. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- drivers/clk/tegra/clk-periph-gate.c | 3 +++ 1 file changed, 3 insertions(+)