From patchwork Wed Mar 15 14:27:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel FERNANDEZ X-Patchwork-Id: 9625865 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C37006048C for ; Wed, 15 Mar 2017 14:47:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B6C7A25223 for ; Wed, 15 Mar 2017 14:47:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AB5ED26B41; Wed, 15 Mar 2017 14:47:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D5FA25223 for ; Wed, 15 Mar 2017 14:47:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753425AbdCOO27 (ORCPT ); Wed, 15 Mar 2017 10:28:59 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:3447 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753126AbdCOO2d (ORCPT ); Wed, 15 Mar 2017 10:28:33 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id v2FERdlQ005448; Wed, 15 Mar 2017 15:27:59 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-.pphosted.com with ESMTP id 296gv2qxhe-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 15 Mar 2017 15:27:59 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DCD4C38; Wed, 15 Mar 2017 14:27:58 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag4node2.st.com [10.75.127.11]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A169128D3; Wed, 15 Mar 2017 14:27:58 +0000 (GMT) Received: from localhost (10.75.127.50) by SFHDAG4NODE2.st.com (10.75.127.11) with Microsoft SMTP Server (TLS) id 15.0.1178.4; Wed, 15 Mar 2017 15:27:57 +0100 From: To: Michael Turquette , Stephen Boyd , Maxime Coquelin , Alexandre Torgue , Nicolas Pitre , Arnd Bergmann , , , CC: , , , Subject: [PATCH 2/2] clk: stm32f4: fix timeout management for pll and ready gate Date: Wed, 15 Mar 2017 15:27:51 +0100 Message-ID: <1489588071-18164-3-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1489588071-18164-1-git-send-email-gabriel.fernandez@st.com> References: <1489588071-18164-1-git-send-email-gabriel.fernandez@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG4NODE2.st.com (10.75.127.11) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-15_05:, , signatures=0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gabriel Fernandez Use a classic polling to test bit ready. And the shift of the bit ready of LSE & LSI were wrongs. Signed-off-by: Gabriel Fernandez --- drivers/clk/clk-stm32f4.c | 43 +++++++++++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index cf9449b3..68e2a4e 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -531,19 +531,26 @@ static int stm32f4_pll_is_enabled(struct clk_hw *hw) return clk_gate_ops.is_enabled(hw); } +#define PLL_TIMEOUT 10000 + static int stm32f4_pll_enable(struct clk_hw *hw) { struct clk_gate *gate = to_clk_gate(hw); struct stm32f4_pll *pll = to_stm32f4_pll(gate); - int ret = 0; - unsigned long reg; + int bit_status; + unsigned int timeout = PLL_TIMEOUT; - ret = clk_gate_ops.enable(hw); + if (clk_gate_ops.is_enabled(hw)) + return 0; + + clk_gate_ops.enable(hw); - ret = readl_relaxed_poll_timeout_atomic(base + STM32F4_RCC_CR, reg, - reg & (1 << pll->bit_rdy_idx), 0, 10000); + do { + bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx)); - return ret; + } while (bit_status && --timeout); + + return bit_status; } static void stm32f4_pll_disable(struct clk_hw *hw) @@ -834,24 +841,32 @@ struct stm32_rgate { u8 bit_rdy_idx; }; -#define RTC_TIMEOUT 1000000 +#define RGATE_TIMEOUT 50000 static int rgclk_enable(struct clk_hw *hw) { struct clk_gate *gate = to_clk_gate(hw); struct stm32_rgate *rgate = to_rgclk(gate); - u32 reg; - int ret; + int bit_status; + unsigned int timeout = RGATE_TIMEOUT; + + if (clk_gate_ops.is_enabled(hw)) + return 0; disable_power_domain_write_protection(); clk_gate_ops.enable(hw); - ret = readl_relaxed_poll_timeout_atomic(gate->reg, reg, - reg & rgate->bit_rdy_idx, 1000, RTC_TIMEOUT); + do { + bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx)); + if (bit_status) + udelay(100); + + } while (bit_status && --timeout); enable_power_domain_write_protection(); - return ret; + + return bit_status; } static void rgclk_disable(struct clk_hw *hw) @@ -1533,7 +1548,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) } clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0, - base + STM32F4_RCC_CSR, 0, 2, 0, &stm32f4_clk_lock); + base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock); if (IS_ERR(clks[CLK_LSI])) { pr_err("Unable to register lsi clock\n"); @@ -1541,7 +1556,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) } clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0, - base + STM32F4_RCC_BDCR, 0, 2, 0, &stm32f4_clk_lock); + base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock); if (IS_ERR(clks[CLK_LSE])) { pr_err("Unable to register lse clock\n");