From patchwork Fri Mar 17 15:02:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 9630895 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BE61F60245 for ; Fri, 17 Mar 2017 15:05:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B6159285A9 for ; Fri, 17 Mar 2017 15:05:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AA669286B6; Fri, 17 Mar 2017 15:05:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4D4A6285A9 for ; Fri, 17 Mar 2017 15:05:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751391AbdCQPFZ (ORCPT ); Fri, 17 Mar 2017 11:05:25 -0400 Received: from mail-pg0-f52.google.com ([74.125.83.52]:33907 "EHLO mail-pg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751079AbdCQPEX (ORCPT ); Fri, 17 Mar 2017 11:04:23 -0400 Received: by mail-pg0-f52.google.com with SMTP id 21so9750200pgg.1 for ; Fri, 17 Mar 2017 08:03:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=9X1RacVAzSXKsWvS2e4e2ehj1MFIxr+OfNyxCovT4eo=; b=ZI87j0y81r45CUkRT0svQLr0+bTUPW7LXsfBNDUfVb2nuzNtXX+oBIRwbg7M2IUMpX f4iuajK/XD6nn5n1mo3diB/bBxJNd9nSpA56z32504K7YNZfhrkv770dSWzQUC5Nlow7 rvuJKhnVtufkEQqVWVmGLLCYW16wjcFE1t06Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=9X1RacVAzSXKsWvS2e4e2ehj1MFIxr+OfNyxCovT4eo=; b=TLV9rThdU/rkaCstzYXYR0ycNobqBbZf4niFyaCJ20fmmPEeYbf2kaopJELOOsRtkT QFRgkgGPRDd8/EHfxkbshOx6tGVzYR4+dxoi/E7b13F1O0TsoZ26323usi1wh5BPlB2I C/UancitTJ8BhGNCoF86sGTwBxo3k7aM0kfhjha/eiy93puSdac5NwQldjTJK0fCUDcB 13kDoIWMuGbgSTymtkKZUnaJjbjllAKAOSp0Jb0qc4yjUXQkawcLJL+1LEzRZIM14Z2D v3EkUbNWv7uBS52KKHNl13w3GQSono4ZTbsfZGSG7iVAQRBSPz4npKMezH+EFFZy1Wmw +Iww== X-Gm-Message-State: AFeK/H1dIrbTqEVgoReVS2IsysnelW76If0I2owTBHigRuT4WL9JmdquHZzcgWEqVm2KMItx X-Received: by 10.84.231.135 with SMTP id g7mr111621plk.12.1489763030616; Fri, 17 Mar 2017 08:03:50 -0700 (PDT) Received: from localhost.localdomain ([103.230.219.215]) by smtp.gmail.com with ESMTPSA id f125sm17482582pfc.4.2017.03.17.08.03.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Mar 2017 08:03:49 -0700 (PDT) From: Leo Yan To: Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , Andy Gross , David Brown , Michael Turquette , Stephen Boyd , Mathieu Poirier , Leo Yan , Guodong Xu , John Stultz , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, mike.leach@linaro.org, Suzuki.Poulose@arm.com, sudeep.holla@arm.com Subject: [PATCH v4 1/7] coresight: bindings for CPU debug module Date: Fri, 17 Mar 2017 23:02:17 +0800 Message-Id: <1489762943-25849-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489762943-25849-1-git-send-email-leo.yan@linaro.org> References: <1489762943-25849-1-git-send-email-leo.yan@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate debug module and it can support self-hosted debug and external debug. Especially for supporting self-hosted debug, this means the program can access the debug module from mmio region; and usually the mmio region is integrated with coresight. So add document for binding debug component, includes binding to APB clock; and also need specify the CPU node which the debug module is dedicated to specific CPU. Suggested-by: Mike Leach Reviewed-by: Mathieu Poirier Signed-off-by: Leo Yan --- .../bindings/arm/coresight-cpu-debug.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt new file mode 100644 index 0000000..f6855c3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt @@ -0,0 +1,46 @@ +* CoreSight CPU Debug Component: + +CoreSight cpu debug component are compliant with the ARMv8 architecture +reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The +external debug module is mainly used for two modes: self-hosted debug and +external debug, and it can be accessed from mmio region from Coresight +and eventually the debug module connects with CPU for debugging. And the +debug module provides sample-based profiling extension, which can be used +to sample CPU program counter, secure state and exception level, etc; +usually every CPU has one dedicated debug module to be connected. + +Required properties: + +- compatible : should be + * "arm,coresight-cpu-debug"; supplemented with "arm,primecell" + since this driver is using the AMBA bus interface. + +- reg : physical base address and length of the register set. + +- clocks : the clock associated to this component. + +- clock-names : the name of the clock referenced by the code. Since we are + using the AMBA framework, the name of the clock providing + the interconnect should be "apb_pclk" and the clock is + mandatory. The interface between the debug logic and the + processor core is clocked by the internal CPU clock, so it + is enabled with CPU clock by default. + +- cpu : the cpu phandle the debug module is affined to. When omitted + the module is considered to belong to CPU0. + +Optional properties: + +- power-domains: a phandle to power domain node for debug module. We can + use "nohlt" to ensure CPU power domain is enabled. + + +Example: + + debug@f6590000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + };