From patchwork Wed Mar 22 10:32:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 9638449 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D870160327 for ; Wed, 22 Mar 2017 10:33:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B9347272F9 for ; Wed, 22 Mar 2017 10:33:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AE2E428451; Wed, 22 Mar 2017 10:33:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9B4A32840E for ; Wed, 22 Mar 2017 10:33:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933950AbdCVKdj (ORCPT ); Wed, 22 Mar 2017 06:33:39 -0400 Received: from mail-wr0-f172.google.com ([209.85.128.172]:33109 "EHLO mail-wr0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758893AbdCVKc7 (ORCPT ); Wed, 22 Mar 2017 06:32:59 -0400 Received: by mail-wr0-f172.google.com with SMTP id y90so9609306wrb.0 for ; Wed, 22 Mar 2017 03:32:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kytA2qENWVVeorPBo8+3mPKSnNnKolxWLZQrFj/y+QY=; b=ipcp/sIQXNeEu7sQAhhis92DTZHul+HCPo9FSfjo+RGK9MyvW85qpl+FGKmrvprHqJ S10NOGjb3FR/1BCB9MQL4NtFopp+Oky+Y8VEO9zzs2vAS+oPXzJrqtl3vUVajBGq1808 HIg87e5H1hfGxwxiINpJMuKmiW1fy/MGIauTekVt+MBDgkAKxvz5+UVbhPr0cGEr7pOJ Gp2jJs/kBSKoAJbZDJdRlsGLpI1JE+l/kKWIW98EGEX8zhuj271drHn/aStiW2BroAb7 PRr+Vh9AdVdcQG4PCvMkaIQpiX1zLeBM95Bb5EIbFxWpv9S+ba5ZmfKsDkAVoNLQ7CUd 7GbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kytA2qENWVVeorPBo8+3mPKSnNnKolxWLZQrFj/y+QY=; b=aWVEZti7i35xulMrD28X9ut/ezv9JZiwNZsKkZdVHgfiwaXFJhHGcqQEaxcZ8Gupvb l2SRkGdjBGqRawvGfePdR8zZSD91QezMl4esQvi0/rr7j0Vk9M2K+rP8dkisp6HPMoim F31sDS3W0pkVOB79x/Qcaat+2HUZ/JZLV+7nPAUQm8uFjs2y7WYLmCQc2UnQ4+z+I7C7 9+TDCznJ/h1pJpD0r65RkUiwfqxnwpziDVdhdwaO6qhFjzI8gi3BRS7ScouG83ugk22t EXdSR0brNaSJ6uB8ZKC05FjWFC0WOmZs3pUSsKKl1I8ppQ/eoVVezXwNgiOb+kQw9XsL /aNw== X-Gm-Message-State: AFeK/H0J55zSNQH3zVdIwqjDfQ+9voI5ZBwkw7TAOvSv7IuwibLPRahK0TvHw+MMl98Yxx6N X-Received: by 10.223.164.85 with SMTP id e21mr35398269wra.58.1490178756418; Wed, 22 Mar 2017 03:32:36 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id 53sm1285309wrt.52.2017.03.22.03.32.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Mar 2017 03:32:35 -0700 (PDT) From: Neil Armstrong To: mturquette@baylibre.com, sboyd@codeaurora.org, carlo@caione.org, khilman@baylibre.com Cc: Neil Armstrong , linux-clk@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] clk: meson: Add support for parameters for specific PLLs Date: Wed, 22 Mar 2017 11:32:23 +0100 Message-Id: <1490178747-14837-2-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490178747-14837-1-git-send-email-narmstrong@baylibre.com> References: <1490178747-14837-1-git-send-email-narmstrong@baylibre.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In recent Amlogic GXBB, GXL and GXM SoCs, the GP0 PLL needs some specific parameters in order to initialize and lock correctly. This patch adds an optional PARAM table used to initialize the PLL to a default value with it's parameters in order to achieve to desired frequency. The GP0 PLL in GXBB, GXL/GXM also needs some tweaks in the initialization steps, and these are exposed along the PARAM table. Signed-off-by: Neil Armstrong --- drivers/clk/meson/clk-pll.c | 53 +++++++++++++++++++++++++++++++++++++++++++-- drivers/clk/meson/clkc.h | 23 ++++++++++++++++++++ 2 files changed, 74 insertions(+), 2 deletions(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 4adc1e8..0134155 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -116,6 +116,30 @@ static const struct pll_rate_table *meson_clk_get_pll_settings(struct meson_clk_ return NULL; } +/* Specific wait loop for GXL/GXM GP0 PLL */ +static int meson_clk_pll_wait_lock_reset(struct meson_clk_pll *pll, + struct parm *p_n) +{ + int delay = 100; + u32 reg; + + while (delay > 0) { + reg = readl(pll->base + p_n->reg_off); + writel(reg | MESON_PLL_RESET, pll->base + p_n->reg_off); + udelay(10); + writel(reg & ~MESON_PLL_RESET, pll->base + p_n->reg_off); + + /* This delay comes from AMLogic tree clk-gp0-gxl driver */ + mdelay(1); + + reg = readl(pll->base + p_n->reg_off); + if (reg & MESON_PLL_LOCK) + return 0; + delay--; + } + return -ETIMEDOUT; +} + static int meson_clk_pll_wait_lock(struct meson_clk_pll *pll, struct parm *p_n) { @@ -132,6 +156,15 @@ static int meson_clk_pll_wait_lock(struct meson_clk_pll *pll, return -ETIMEDOUT; } +static void meson_clk_pll_init_params(struct meson_clk_pll *pll) +{ + int i; + + for (i = 0 ; i < pll->params.params_count ; ++i) + writel(pll->params.params_table[i].value, + pll->base + pll->params.params_table[i].reg_off); +} + static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -151,10 +184,16 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, if (!rate_set) return -EINVAL; + /* Initialize the PLL in a clean state if specified */ + if (pll->params.params_count) + meson_clk_pll_init_params(pll); + /* PLL reset */ p = &pll->n; reg = readl(pll->base + p->reg_off); - writel(reg | MESON_PLL_RESET, pll->base + p->reg_off); + /* If no_init_reset is provided, avoid resetting at this point */ + if (!pll->params.no_init_reset) + writel(reg | MESON_PLL_RESET, pll->base + p->reg_off); reg = PARM_SET(p->width, p->shift, reg, rate_set->n); writel(reg, pll->base + p->reg_off); @@ -184,7 +223,17 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, } p = &pll->n; - ret = meson_clk_pll_wait_lock(pll, p); + /* If clear_reset_for_lock is provided, remove the reset bit here */ + if (pll->params.clear_reset_for_lock) { + reg = readl(pll->base + p->reg_off); + writel(reg & ~MESON_PLL_RESET, pll->base + p->reg_off); + } + + /* If reset_lock_loop, use a special loop including resetting */ + if (pll->params.reset_lock_loop) + ret = meson_clk_pll_wait_lock_reset(pll, p); + else + ret = meson_clk_pll_wait_lock(pll, p); if (ret) { pr_warn("%s: pll did not lock, trying to restore old rate %lu\n", __func__, old_rate); diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index ad25467..b0c9999 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -62,6 +62,28 @@ struct pll_rate_table { .frac = (_frac), \ } \ +struct pll_params_table { + unsigned int reg_off; + unsigned int value; +}; + +#define PLL_PARAM(_reg, _val) \ + { \ + .reg_off = (_reg), \ + .value = (_val), \ + } + +struct pll_setup_params { + struct pll_params_table *params_table; + unsigned int params_count; + /* Workaround for GP0, do not reset before configuring */ + bool no_init_reset; + /* Workaround for GP0, unreset right before checking for lock */ + bool clear_reset_for_lock; + /* Workaround for GXL GP0, reset in the lock checking loop */ + bool reset_lock_loop; +}; + struct meson_clk_pll { struct clk_hw hw; void __iomem *base; @@ -70,6 +92,7 @@ struct meson_clk_pll { struct parm frac; struct parm od; struct parm od2; + const struct pll_setup_params params; const struct pll_rate_table *rate_table; unsigned int rate_count; spinlock_t *lock;