diff mbox

[02/10] clk: renesas: Add r8a7790 CPG Core Clock Definitions

Message ID 1493139200-27396-3-git-send-email-geert+renesas@glider.be (mailing list archive)
State Superseded
Headers show

Commit Message

Geert Uytterhoeven April 25, 2017, 4:53 p.m. UTC 
Add all R-Car H2 Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2a ("List of Clocks [R-Car H2]") of the R-Car Gen2 Hardware
User's Manual rev. 2.00.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 include/dt-bindings/clock/r8a7790-cpg-mssr.h | 52 ++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a7790-cpg-mssr.h

Comments

Niklas Söderlund April 28, 2017, 12:38 p.m. UTC | #1 
Hi Geert,

On 2017-04-25 18:53:12 +0200, Geert Uytterhoeven wrote:
> Add all R-Car H2 Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2a ("List of Clocks [R-Car H2]") of the R-Car Gen2 Hardware
> User's Manual rev. 2.00.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  include/dt-bindings/clock/r8a7790-cpg-mssr.h | 52 ++++++++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
>  create mode 100644 include/dt-bindings/clock/r8a7790-cpg-mssr.h
> 
> diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
> new file mode 100644
> index 0000000000000000..1625b8bf34822b6e
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
> @@ -0,0 +1,52 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7790 CPG Core Clocks */
> +#define R8A7790_CLK_Z			0
> +#define R8A7790_CLK_Z2			1
> +#define R8A7790_CLK_ZG			2
> +#define R8A7790_CLK_ZTR			3
> +#define R8A7790_CLK_ZTRD2		4
> +#define R8A7790_CLK_ZT			5
> +#define R8A7790_CLK_ZX			6
> +#define R8A7790_CLK_ZS			7
> +#define R8A7790_CLK_HP			8
> +#define R8A7790_CLK_I			9
> +#define R8A7790_CLK_B			10
> +#define R8A7790_CLK_LB			11
> +#define R8A7790_CLK_P			12
> +#define R8A7790_CLK_CL			13
> +#define R8A7790_CLK_M2			14
> +#define R8A7790_CLK_ADSP		15
> +#define R8A7790_CLK_IMP			16
> +#define R8A7790_CLK_ZB3			17
> +#define R8A7790_CLK_ZB3D2		18
> +#define R8A7790_CLK_DDR			19
> +#define R8A7790_CLK_SDH			20
> +#define R8A7790_CLK_SD0			21
> +#define R8A7790_CLK_SD1			22
> +#define R8A7790_CLK_SD2			23
> +#define R8A7790_CLK_SD3			24
> +#define R8A7790_CLK_MMC0		25
> +#define R8A7790_CLK_MMC1		26
> +#define R8A7790_CLK_MP			27
> +#define R8A7790_CLK_SSP			28
> +#define R8A7790_CLK_SSPRS		29
> +#define R8A7790_CLK_QSPI		30
> +#define R8A7790_CLK_CP			31
> +#define R8A7790_CLK_RCAN		32
> +#define R8A7790_CLK_R			33
> +#define R8A7790_CLK_OSC			34

The last two are called RCLR and OSCCLK in the Table 7.2a ("List of 
Clocks [R-Car H2]"). I'm sure this is intentional on your side, and if 
so:

Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
> -- 
> 2.7.4
>
Geert Uytterhoeven April 28, 2017, 12:45 p.m. UTC | #2 
Hi Niklas,

On Fri, Apr 28, 2017 at 2:38 PM, Niklas Söderlund
<niklas.soderlund@ragnatech.se> wrote:
>
> On 2017-04-25 18:53:12 +0200, Geert Uytterhoeven wrote:
>> Add all R-Car H2 Clock Pulse Generator Core Clock Outputs, as listed in
>> Table 7.2a ("List of Clocks [R-Car H2]") of the R-Car Gen2 Hardware
>> User's Manual rev. 2.00.
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

>> --- /dev/null
>> +++ b/include/dt-bindings/clock/r8a7790-cpg-mssr.h

>> +#define R8A7790_CLK_R                        33
>> +#define R8A7790_CLK_OSC                      34
>
> The last two are called RCLR and OSCCLK in the Table 7.2a ("List of
> Clocks [R-Car H2]"). I'm sure this is intentional on your side, and if
> so:

It's a bit silly to have two clocks with "clk" in their name, while
all others don't.
We did the same on R-Car Gen3.

> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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diff mbox

Patch

diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
new file mode 100644
index 0000000000000000..1625b8bf34822b6e
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
@@ -0,0 +1,52 @@ 
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7790 CPG Core Clocks */
+#define R8A7790_CLK_Z			0
+#define R8A7790_CLK_Z2			1
+#define R8A7790_CLK_ZG			2
+#define R8A7790_CLK_ZTR			3
+#define R8A7790_CLK_ZTRD2		4
+#define R8A7790_CLK_ZT			5
+#define R8A7790_CLK_ZX			6
+#define R8A7790_CLK_ZS			7
+#define R8A7790_CLK_HP			8
+#define R8A7790_CLK_I			9
+#define R8A7790_CLK_B			10
+#define R8A7790_CLK_LB			11
+#define R8A7790_CLK_P			12
+#define R8A7790_CLK_CL			13
+#define R8A7790_CLK_M2			14
+#define R8A7790_CLK_ADSP		15
+#define R8A7790_CLK_IMP			16
+#define R8A7790_CLK_ZB3			17
+#define R8A7790_CLK_ZB3D2		18
+#define R8A7790_CLK_DDR			19
+#define R8A7790_CLK_SDH			20
+#define R8A7790_CLK_SD0			21
+#define R8A7790_CLK_SD1			22
+#define R8A7790_CLK_SD2			23
+#define R8A7790_CLK_SD3			24
+#define R8A7790_CLK_MMC0		25
+#define R8A7790_CLK_MMC1		26
+#define R8A7790_CLK_MP			27
+#define R8A7790_CLK_SSP			28
+#define R8A7790_CLK_SSPRS		29
+#define R8A7790_CLK_QSPI		30
+#define R8A7790_CLK_CP			31
+#define R8A7790_CLK_RCAN		32
+#define R8A7790_CLK_R			33
+#define R8A7790_CLK_OSC			34
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */