diff mbox

[v2] clk: sunxi-ng: v3s: Fix usb otg device reset bit

Message ID 1493980317-39775-1-git-send-email-iemdey@gmail.com (mailing list archive)
State Accepted
Headers show

Commit Message

Yong Deng May 5, 2017, 10:31 a.m. UTC 
V3S's usb otg device reset bit should be 24, not 23.

Signed-off-by: Yong Deng <iemdey@gmail.com>
Reviewed-By: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v2:
- Fix commit format

 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Maxime Ripard May 5, 2017, 8:04 p.m. UTC | #1 
Hi,

On Fri, May 05, 2017 at 06:31:57PM +0800, Yong Deng wrote:
> V3S's usb otg device reset bit should be 24, not 23.
> 
> Signed-off-by: Yong Deng <iemdey@gmail.com>
> Reviewed-By: Icenowy Zheng <icenowy@aosc.io>

Applied, thanks.
Maxime
Icenowy Zheng May 6, 2017, 2:51 p.m. UTC | #2 
在 2017-05-06 04:04，Maxime Ripard 写道：
> Hi,
> 
> On Fri, May 05, 2017 at 06:31:57PM +0800, Yong Deng wrote:
>> V3S's usb otg device reset bit should be 24, not 23.
>> 
>> Signed-off-by: Yong Deng <iemdey@gmail.com>
>> Reviewed-By: Icenowy Zheng <icenowy@aosc.io>
> 
> Applied, thanks.
> Maxime

Maybe it should also apply to 4.11 stable?

Cc: stable@vger.kernel.org
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Maxime Ripard May 9, 2017, 7:09 p.m. UTC | #3 
On Sat, May 06, 2017 at 10:51:25PM +0800, icenowy@aosc.io wrote:
> 在 2017-05-06 04:04，Maxime Ripard 写道：
> > Hi,
> > 
> > On Fri, May 05, 2017 at 06:31:57PM +0800, Yong Deng wrote:
> > > V3S's usb otg device reset bit should be 24, not 23.
> > > 
> > > Signed-off-by: Yong Deng <iemdey@gmail.com>
> > > Reviewed-By: Icenowy Zheng <icenowy@aosc.io>
> > 
> > Applied, thanks.
> > Maxime
> 
> Maybe it should also apply to 4.11 stable?
> 
> Cc: stable@vger.kernel.org

I just added it, thanks!
Maxime
diff mbox

Patch

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index e58706b..6297add 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -537,7 +537,7 @@  static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
 	[RST_BUS_EMAC]		=  { 0x2c0, BIT(17) },
 	[RST_BUS_HSTIMER]	=  { 0x2c0, BIT(19) },
 	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
-	[RST_BUS_OTG]		=  { 0x2c0, BIT(23) },
+	[RST_BUS_OTG]		=  { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(26) },
 	[RST_BUS_OHCI0]		=  { 0x2c0, BIT(29) },