From patchwork Sat May 6 11:54:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 9714675 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4391E60390 for ; Sat, 6 May 2017 11:58:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 520D32863C for ; Sat, 6 May 2017 11:58:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 409EB286A4; Sat, 6 May 2017 11:58:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C9EC2286B3 for ; Sat, 6 May 2017 11:58:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753271AbdEFL55 (ORCPT ); Sat, 6 May 2017 07:57:57 -0400 Received: from mail-wr0-f176.google.com ([209.85.128.176]:32932 "EHLO mail-wr0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752723AbdEFL5n (ORCPT ); Sat, 6 May 2017 07:57:43 -0400 Received: by mail-wr0-f176.google.com with SMTP id w50so15829088wrc.0 for ; Sat, 06 May 2017 04:57:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JtMfkueFeAcckT43XWCftniNE7QmwhismdvCbxr5m7w=; b=XW30SaQlDNGJ3F6bBKRX37kdsyc6j1afxlXy85q/8wZ1oLdgmfcE7F+mR6kwh7AFAT t75ajRPOsf8MnTRuRKApU1UoUzDfSdVGCNOXfxjn0tgon4eu/W534Na5r2aK09hSgLHZ xnTbV0VyjQ1QkEltihE7XnF/tSYcBudIJu2Fk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JtMfkueFeAcckT43XWCftniNE7QmwhismdvCbxr5m7w=; b=dA/BKi5SQ6l6y9ju1aDM4/IuGBwogpLOjb8jORoKt6QgwgOtpPqRoeG0EsqlwosKyo NUHxV9mjzuqYxJxRkRh6hZOFbKjR6sHGaYElWpjKEhM/DBYvHOWohOXjI7prszN2sF7p Ggj+Htvr1NtVygOuiJ0sjNgAs+CN1GML++w2YDKC0ctxAZXoyv2oLZVh4pcVKP7fkX+U bI45Yx7qMmzQaO611CFCXyzXsIdMm8ZWuyTJYhscgMGcVJSiUQWjcesaRMQSmvvBimZI TD1EuSE9rcGg29v34PXGTsY6HyDccYDnCVfdJwSwYkeiHCpsnBC6t6q+mb3cJxG6CSAR R4TA== X-Gm-Message-State: AN3rC/5YNYGsEzrlFm28Pnv+6OWc9935DiuyQ/d6sl8UiApFOaK4Z0oi xAbY2B+4EUD4fu9L X-Received: by 10.223.139.146 with SMTP id o18mr28932824wra.146.1494071861512; Sat, 06 May 2017 04:57:41 -0700 (PDT) Received: from anup-HP-Compaq-8100-Elite-CMT-PC.dhcp.avagotech.net ([192.19.237.250]) by smtp.gmail.com with ESMTPSA id 8sm7775789wrb.55.2017.05.06.04.57.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 06 May 2017 04:57:41 -0700 (PDT) From: Anup Patel To: Rob Herring , Mark Rutland , Michael Turquette Cc: Catalin Marinas , Will Deacon , Ray Jui , Scott Branden , Jon Mason , Florian Fainelli , Oza Pawandeep , Srinath Mannam , Pramod Kumar , Sandeep Tripathy , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, Anup Patel Subject: [PATCH 11/11] arm64: dts: Add PWM and SDHCI DT nodes for Stingray SOC Date: Sat, 6 May 2017 17:24:46 +0530 Message-Id: <1494071686-19098-12-git-send-email-anup.patel@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1494071686-19098-1-git-send-email-anup.patel@broadcom.com> References: <1494071686-19098-1-git-send-email-anup.patel@broadcom.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinath Mannam The Stingray SoC has two instances of SDHCI controller and one instance of iProc PWM. Let's enable above mentioned devices in Stingray DT. Signed-off-by: Srinath Mannam Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- .../boot/dts/broadcom/stingray/bcm958742-base.dtsi | 39 ++++++++++++++++++++++ .../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 28 ++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi index 3250d09..a491ce9 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi @@ -52,6 +52,28 @@ serial2 = &uart2; serial3 = &uart3; }; + + sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl { + compatible = "regulator-gpio"; + regulator-name = "sdio0_vddo_ctrl_reg"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pca9505 18 0>; + states = <3300000 0x0 + 1800000 0x1>; + }; + + sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl { + compatible = "regulator-gpio"; + regulator-name = "sdio1_vddo_ctrl_reg"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pca9505 19 0>; + states = <3300000 0x0 + 1800000 0x1>; + }; }; &memory { /* Default DRAM banks */ @@ -63,6 +85,10 @@ status = "okay"; }; +&pwm { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -99,3 +125,16 @@ #size-cells = <1>; }; }; + +&sdio0 { + vqmmc-supply = <&sdio0_vddo_ctrl_reg>; + non-removable; + full-pwr-cycle; + status = "okay"; +}; + +&sdio1 { + vqmmc-supply = <&sdio1_vddo_ctrl_reg>; + full-pwr-cycle; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 36b8ced..d5e1944 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -266,6 +266,14 @@ gpio-controller; }; + pwm: pwm@68910000{ + compatible = "brcm,iproc-pwm"; + reg = <0x68910000 0x1000>; + clocks = <&crmu_ref25m>; + #pwm-cells = <3>; + status = "disabled"; + }; + i2c0: i2c@689b0000 { compatible = "brcm,iproc-i2c"; reg = <0x689b0000 0x100>; @@ -425,5 +433,25 @@ brcm,nand-has-wp; status = "disabled"; }; + + sdio0: sdhci@68cf1000 { + compatible = "brcm,sdhci-iproc"; + reg = <0x68cf1000 0x100>; + interrupts = ; + bus-width = <8>; + clocks = <&sdio0_clk>; + iommus = <&smmu 0x6002 0x0000>; + status = "disabled"; + }; + + sdio1: sdhci@68cf2000 { + compatible = "brcm,sdhci-iproc"; + reg = <0x68cf2000 0x100>; + interrupts = ; + bus-width = <8>; + clocks = <&sdio1_clk>; + iommus = <&smmu 0x6003 0x0000>; + status = "disabled"; + }; }; };