From patchwork Sat May 6 11:54:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 9714635 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9C8A36038F for ; Sat, 6 May 2017 11:56:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A9DAF28607 for ; Sat, 6 May 2017 11:56:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9E83B286B3; Sat, 6 May 2017 11:56:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 09EB5286A4 for ; Sat, 6 May 2017 11:56:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753284AbdEFL4N (ORCPT ); Sat, 6 May 2017 07:56:13 -0400 Received: from mail-wr0-f169.google.com ([209.85.128.169]:33878 "EHLO mail-wr0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753193AbdEFL4F (ORCPT ); Sat, 6 May 2017 07:56:05 -0400 Received: by mail-wr0-f169.google.com with SMTP id l9so15768568wre.1 for ; Sat, 06 May 2017 04:56:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Apqe/dr72Q9QSLxAghgWMsoDzBAlZ9f6bH1IDLT0SVk=; b=TIPykq5OCmt6d9rSwi7gyXYgdXZMVx6Ze4qfQfnthqG24SuJecpxB4wIdWPR2j6SaD A1OOe9r11ptyCAHiE06BL8KBUrpEkETtgSGTn0sKhY2lmDVrMVR+chFrNJe7WA64718h WqyDnPMS4sVqDDvVbIPwPVG8hspuvQsvZLUgE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Apqe/dr72Q9QSLxAghgWMsoDzBAlZ9f6bH1IDLT0SVk=; b=q8jz79wryIeTTqD7v+kspnSDNFrAdrJt9UFxfaN7NS2aRdRMLjsm56KRzIDvzvlTMh vMcThmBbr4jWkktISlzj2sIzQ5oBZlNUta7u+wrsF82I2POgPiA15QmAbL40GiTZqihh WCudCxwvcl87QCq7qxANctGp2k3IbtarUrYjoYoSt7M0pF0Hnx42NqDyn/3XHCn2Palf MPZYNss1AQH4+IqFvK7Ca2OazWofQE+bHGABN16fAOU0pUwSqP9qKpGbLwfU7I7eP23C sBCDsKwoLbm2TlRMnS5TrDO2pa2YvJQEBXpShf6c/pQB1/rb7g7WJlPIMsyPzrXqXZmH j8/g== X-Gm-Message-State: AN3rC/5lTIt1DHcm6amXaDck0yK4R878tkqVZ4Hu69IYfKcCQ+Akt0sz +c9jqESMzHybEnxo X-Received: by 10.223.153.195 with SMTP id y61mr35115348wrb.96.1494071763863; Sat, 06 May 2017 04:56:03 -0700 (PDT) Received: from anup-HP-Compaq-8100-Elite-CMT-PC.dhcp.avagotech.net ([192.19.237.250]) by smtp.gmail.com with ESMTPSA id 8sm7775789wrb.55.2017.05.06.04.55.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 06 May 2017 04:56:03 -0700 (PDT) From: Anup Patel To: Rob Herring , Mark Rutland , Michael Turquette Cc: Catalin Marinas , Will Deacon , Ray Jui , Scott Branden , Jon Mason , Florian Fainelli , Oza Pawandeep , Srinath Mannam , Pramod Kumar , Sandeep Tripathy , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com Subject: [PATCH 02/11] dt-bindings: clk: Extend binding doc for Stingray SOC Date: Sat, 6 May 2017 17:24:37 +0530 Message-Id: <1494071686-19098-3-git-send-email-anup.patel@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1494071686-19098-1-git-send-email-anup.patel@broadcom.com> References: <1494071686-19098-1-git-send-email-anup.patel@broadcom.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sandeep Tripathy Update iproc clock dt-binding documentation with Stingray pll and clock details. Signed-off-by: Sandeep Tripathy Reviewed-by: Ray Jui Reviewed-by: Scott Branden Acked-by: Rob Herring --- .../bindings/clock/brcm,iproc-clocks.txt | 76 ++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index 6f66e9a..f2c5f0e4a 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -219,3 +219,79 @@ BCM63138 -------- PLL and leaf clock compatible strings for BCM63138 are: "brcm,bcm63138-armpll" + +Stingray +----------- +PLL and leaf clock compatible strings for Stingray are: + "brcm,sr-genpll0" + "brcm,sr-genpll1" + "brcm,sr-genpll2" + "brcm,sr-genpll3" + "brcm,sr-genpll4" + "brcm,sr-genpll5" + "brcm,sr-genpll6" + + "brcm,sr-lcpll0" + "brcm,sr-lcpll1" + "brcm,sr-lcpll-pcie" + + +The following table defines the set of PLL/clock index and ID for Stingray. +These clock IDs are defined in: + "include/dt-bindings/clock/bcm-sr.h" + + Clock Source Index ID + --- ----- ----- --------- + crystal N/A N/A N/A + crmu_ref25m crystal N/A N/A + + genpll0 crystal 0 BCM_SR_GENPLL0 + clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK + clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK + clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK + clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK + clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK + clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK + + genpll1 crystal 0 BCM_SR_GENPLL1 + clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK + clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK + + genpll2 crystal 0 BCM_SR_GENPLL2 + clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK + clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK + clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK + clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK + clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH + + genpll3 crystal 0 BCM_SR_GENPLL3 + clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK + clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK + + genpll4 crystal 0 BCM_SR_GENPLL4 + ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK + clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK + noc_clk genpll4 3 BCM_SR_GENPLL4_NOC_CLK + clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK + clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK + + + genpll5 crystal 0 BCM_SR_GENPLL5 + fs4_hf_clk genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK + crypto_ae_clk genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK + raid_ae_clk genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK + + genpll6 crystal 0 BCM_SR_GENPLL6 + 48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK + + lcpll0 crystal 0 BCM_SR_LCPLL0 + clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK + clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK + clk_usb_ref lcpll0 3 BCM_SR_LCPLL0_USB_REF_CLK + sata_refpn lcpll0 3 BCM_SR_LCPLL0_SATA_REFPN_CLK + + lcpll1 crystal 0 BCM_SR_LCPLL1 + wan lcpll1 1 BCM_SR_LCPLL0_WAN_CLK + + lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE + pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK