From patchwork Mon May 15 12:02:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 9726789 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 03246601E7 for ; Mon, 15 May 2017 12:04:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E6DD228498 for ; Mon, 15 May 2017 12:04:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DB1FE2898B; Mon, 15 May 2017 12:04:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 43F3E2898D for ; Mon, 15 May 2017 12:04:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964866AbdEOMEA (ORCPT ); Mon, 15 May 2017 08:04:00 -0400 Received: from mail-pg0-f46.google.com ([74.125.83.46]:34592 "EHLO mail-pg0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758318AbdEOMD5 (ORCPT ); Mon, 15 May 2017 08:03:57 -0400 Received: by mail-pg0-f46.google.com with SMTP id u28so59265653pgn.1 for ; Mon, 15 May 2017 05:03:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=De+RHWc6mV12HeBtzgUHh6kc5z3v9qPPs1pKAvRK1eA=; b=fIax7Ae7wUMhupjyu+gsWzMcvcaaQa9eNdOsTjQwAjNJ5zds28EUz+oe8KyVlQsUz4 gvaXHUvn/Lpdx31eVBcqtVmMhiqqnZtyQ6v+NPKFG1rt9sYKpDvDm5zaeyUk9YS6297k S02uVRABa2ISZcWSMl0bTQOgdvfWI/ISwr5EI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=De+RHWc6mV12HeBtzgUHh6kc5z3v9qPPs1pKAvRK1eA=; b=f6tYFFE1cj7Hty4RsJoWgszP+R+tr6LppGuS4VmDwC2aw6nQ67R0sFNhLxbRQTjYeR 7N846bOGXYdzIVH5Fc9US+ZKDePi0Z2+A2J6GVnj6zCElCA/4GjLXailcnEUUAPCYYyM YOkhPwvHt6nlh8aTl+DJ6rYvsZvwrzoLZJwndV118SpCnD7+A4GaxNK5zXzkZKCZAK6b x8QSKe4YcEwvbj0Gwk0AfhJwpn6iYUNUXVaQXb2av2CtdYUnAOGjFaUu5pCwwZU7SLMo 0o+BzdfGbLce1dGEc3CxSORfekBi+7XLwIjdfZnr9NVLfsAtCDnl0g5wGjsO0LmMM636 OowQ== X-Gm-Message-State: AODbwcByeVC5w1VogMlIw+OTmi8ySbcdJmzzMO8QEf0RBJkgS2P5kWzo aQGimI6oTl9GUFEJ X-Received: by 10.98.102.208 with SMTP id s77mr5880947pfj.22.1494849831644; Mon, 15 May 2017 05:03:51 -0700 (PDT) Received: from anup-HP-Compaq-8100-Elite-CMT-PC.dhcp.avagotech.net ([192.19.237.250]) by smtp.gmail.com with ESMTPSA id m12sm4776572pgn.30.2017.05.15.05.03.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 15 May 2017 05:03:51 -0700 (PDT) From: Anup Patel To: Rob Herring , Mark Rutland , Michael Turquette Cc: Catalin Marinas , Will Deacon , Ray Jui , Scott Branden , Jon Mason , Florian Fainelli , Oza Pawandeep , Srinath Mannam , Pramod Kumar , Sandeep Tripathy , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, Anup Patel Subject: [PATCH v2 11/11] arm64: dts: Add PWM and SDHCI DT nodes for Stingray SOC Date: Mon, 15 May 2017 17:32:21 +0530 Message-Id: <1494849741-21294-12-git-send-email-anup.patel@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1494849741-21294-1-git-send-email-anup.patel@broadcom.com> References: <1494849741-21294-1-git-send-email-anup.patel@broadcom.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinath Mannam The Stingray SoC has two instances of SDHCI controller and one instance of iProc PWM. Let's enable above mentioned devices in Stingray DT. Signed-off-by: Srinath Mannam Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- .../boot/dts/broadcom/stingray/bcm958742-base.dtsi | 39 ++++++++++++++++++++++ .../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 28 ++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi index e3f8c89..6185561 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi @@ -46,6 +46,28 @@ serial2 = &uart2; serial3 = &uart3; }; + + sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl { + compatible = "regulator-gpio"; + regulator-name = "sdio0_vddo_ctrl_reg"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pca9505 18 0>; + states = <3300000 0x0 + 1800000 0x1>; + }; + + sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl { + compatible = "regulator-gpio"; + regulator-name = "sdio1_vddo_ctrl_reg"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pca9505 19 0>; + states = <3300000 0x0 + 1800000 0x1>; + }; }; &memory { /* Default DRAM banks */ @@ -57,6 +79,10 @@ status = "okay"; }; +&pwm { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -93,3 +119,16 @@ #size-cells = <1>; }; }; + +&sdio0 { + vqmmc-supply = <&sdio0_vddo_ctrl_reg>; + non-removable; + full-pwr-cycle; + status = "okay"; +}; + +&sdio1 { + vqmmc-supply = <&sdio1_vddo_ctrl_reg>; + full-pwr-cycle; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 6d9c9f8..aa0ecec 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -274,6 +274,14 @@ #include "stingray-pinctrl.dtsi" + pwm: pwm@68910000{ + compatible = "brcm,iproc-pwm"; + reg = <0x00010000 0x1000>; + clocks = <&crmu_ref25m>; + #pwm-cells = <3>; + status = "disabled"; + }; + i2c0: i2c@689b0000 { compatible = "brcm,iproc-i2c"; reg = <0x000b0000 0x100>; @@ -433,5 +441,25 @@ brcm,nand-has-wp; status = "disabled"; }; + + sdio0: sdhci@68cf1000 { + compatible = "brcm,sdhci-iproc"; + reg = <0x003f1000 0x100>; + interrupts = ; + bus-width = <8>; + clocks = <&sdio0_clk>; + iommus = <&smmu 0x6002 0x0000>; + status = "disabled"; + }; + + sdio1: sdhci@68cf2000 { + compatible = "brcm,sdhci-iproc"; + reg = <0x003f2000 0x100>; + interrupts = ; + bus-width = <8>; + clocks = <&sdio1_clk>; + iommus = <&smmu 0x6003 0x0000>; + status = "disabled"; + }; }; };