From patchwork Wed May 17 14:46:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 9731269 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 48D6A602B4 for ; Wed, 17 May 2017 14:47:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3BA5128792 for ; Wed, 17 May 2017 14:47:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 30689287A9; Wed, 17 May 2017 14:47:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AEAF8287AF for ; Wed, 17 May 2017 14:47:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753847AbdEQOrG (ORCPT ); Wed, 17 May 2017 10:47:06 -0400 Received: from mail-pf0-f181.google.com ([209.85.192.181]:35667 "EHLO mail-pf0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752277AbdEQOrE (ORCPT ); Wed, 17 May 2017 10:47:04 -0400 Received: by mail-pf0-f181.google.com with SMTP id n23so8539943pfb.2 for ; Wed, 17 May 2017 07:47:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wJAzihJNdQtMyT+iTeJQtD3nlj+AP+QoQkcKNRMR0+g=; b=LrS5rt9Jv4fbi+ze3JT3roHcI93v+hPDjTT1izYpOYHd5dDtehtE6AVa8cp9ZYcQXc sZYNFRwmEWiOR5LhnJ5G+r09wskSa9DC6f3WcW+Zu5a07Wp+0eMjIW09UdZU13G1NZCr kfDwJFY4YHZqH9uPIdMCCZ5bBGDD6bnMWp3Sw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wJAzihJNdQtMyT+iTeJQtD3nlj+AP+QoQkcKNRMR0+g=; b=TBK7FHpKxw8pxmeP3dbjClLEX948zkIZ3p98avLivc+YGynw/htq9rEVcQmV4Pm9BI WL6AHQ+lliUZw+FNH3FpEjfPbo7UKg2nqHOzhu0aqoXdnWHIyz3AQw16cnQmhFlncutJ rwVZsweXnrPR8tB2qIv5YGAQjGpVF6vgrMuihGj3oU/rmAS+uIM0KKHlv0mqTVsuRn0C 9pJYprugpLxj9OzqXC/Fs/sWJ63eQt5DKpkSVq5okfzTFVJAa2pKFE4kPUuNJ1fy/dRM OX/5yJVSMFCRH4ONdHhyI4c0LQJU8hVNnCvMDNLcgHmuWbpq3pcwLUfqFIgOqGbwNVaH tX1g== X-Gm-Message-State: AODbwcDFogPiFCkxYf7klfTaLjGd4psIP5Vwnqw+/gI0WWs24bvRVfwl +pZ1shfj6IYhNXjW X-Received: by 10.98.11.79 with SMTP id t76mr4201063pfi.104.1495032422962; Wed, 17 May 2017 07:47:02 -0700 (PDT) Received: from localhost.localdomain (li637-108.members.linode.com. [106.186.117.108]) by smtp.gmail.com with ESMTPSA id v9sm4845037pfa.43.2017.05.17.07.46.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 May 2017 07:47:01 -0700 (PDT) From: Leo Yan To: Wei Xu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Guodong Xu , Zhong Kaihua , Zhangfei Gao , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Leo Yan Subject: [PATCH v1 2/2] arm64: dts: add sp804 timer node for Hi3660 Date: Wed, 17 May 2017 22:46:32 +0800 Message-Id: <1495032392-19102-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495032392-19102-1-git-send-email-leo.yan@linaro.org> References: <1495032392-19102-1-git-send-email-leo.yan@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Hi3660 SoC comes with the sp804 timer in addition to the architecture timers. These ones are shutdown when reaching a deep idle states and a backup timer is needed. The sp804 belongs to another power domain and can fulfill the purpose of replacing temporarily an architecture timer when the CPU is idle. Describe it in the device tree, so it can be enabled at boot time. Suggested-by: Daniel Lezcano Acked-by: Daniel Lezcano Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 138fcba..f75c792 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -173,6 +173,17 @@ #clock-cells = <1>; }; + dual_timer0: timer@fff14000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfff14000 0x0 0x1000>; + interrupts = , + ; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + ufs: ufs@ff3b0000 { compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs"; reg = <0x0 0xff3b0000 0x0 0x1000>, /* 0: HCI standard */