From patchwork Mon May 22 04:52:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 9739591 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7DE8460388 for ; Mon, 22 May 2017 04:53:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7256B286A0 for ; Mon, 22 May 2017 04:53:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 67224286BB; Mon, 22 May 2017 04:53:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DD183286A0 for ; Mon, 22 May 2017 04:53:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751647AbdEVExf (ORCPT ); Mon, 22 May 2017 00:53:35 -0400 Received: from mail-pf0-f172.google.com ([209.85.192.172]:34263 "EHLO mail-pf0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751639AbdEVExd (ORCPT ); Mon, 22 May 2017 00:53:33 -0400 Received: by mail-pf0-f172.google.com with SMTP id 9so70161382pfj.1 for ; Sun, 21 May 2017 21:53:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wJAzihJNdQtMyT+iTeJQtD3nlj+AP+QoQkcKNRMR0+g=; b=APp4w2yxZiJQafvp4ZWU28SRYQ+vs1WjXYU4lkfauIoSgiHobEf/9hikmi4Rr6tyd3 gyYCkxXJxiGF0YwrXyyLBpW/NtBgMT9/AaeQrh4Qqvz8gmPy9WDsYIDnu3aErzYcRrJd pCQEdWQFcOMoEyaz5vbRSMNg0YppsjLUN/jZU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wJAzihJNdQtMyT+iTeJQtD3nlj+AP+QoQkcKNRMR0+g=; b=mVydzoHUAWVd7c96E1C3mZkBCm+DfXL6LHQ/z/bh4IPMjPNv75rxbKi5WWETfADNAm 1XNPJvv6meZU8JHiQoSJYHM2ozah+dLcFBuJSrgIVcTj+lW40RZJPhY6d+3yh1SSnLJT NNOkwZN5y0fiMI2wn9LcmgjC55IHnxWZRTV0NYi8cNhIlnH93YuBQxF+tUMYmjwiLsXb ++J7gf6t7UnEtpfGTc2EOTBsbzAVGnZpIXzoHt6fX0vlUjtKwBQ2Ux1fuWa5pYIAqcis EZHOW8/R8JKwyFiLo1Jn5IikPZYQYsquQArijU3tF9U5qNr+FFqhtBGr+G7+qs6XLs9R V0lQ== X-Gm-Message-State: AODbwcBLbxEx6kzJJuuklItRDgL9b2r+C9Dm1VVapF4LrFbfr0Vusa1F Ys80AW4oWHVB5T8O X-Received: by 10.84.228.201 with SMTP id y9mr26942036pli.13.1495428797525; Sun, 21 May 2017 21:53:17 -0700 (PDT) Received: from localhost.localdomain (li637-108.members.linode.com. [106.186.117.108]) by smtp.gmail.com with ESMTPSA id s68sm28837594pgc.5.2017.05.21.21.53.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 21 May 2017 21:53:16 -0700 (PDT) From: Leo Yan To: Wei Xu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Zhangfei Gao , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Guodong Xu , Haojian Zhuang Cc: Leo Yan Subject: [PATCH v3 2/2] arm64: dts: add sp804 timer node for Hi3660 Date: Mon, 22 May 2017 12:52:28 +0800 Message-Id: <1495428748-11153-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495428748-11153-1-git-send-email-leo.yan@linaro.org> References: <1495428748-11153-1-git-send-email-leo.yan@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Hi3660 SoC comes with the sp804 timer in addition to the architecture timers. These ones are shutdown when reaching a deep idle states and a backup timer is needed. The sp804 belongs to another power domain and can fulfill the purpose of replacing temporarily an architecture timer when the CPU is idle. Describe it in the device tree, so it can be enabled at boot time. Suggested-by: Daniel Lezcano Acked-by: Daniel Lezcano Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 138fcba..f75c792 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -173,6 +173,17 @@ #clock-cells = <1>; }; + dual_timer0: timer@fff14000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfff14000 0x0 0x1000>; + interrupts = , + ; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + ufs: ufs@ff3b0000 { compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs"; reg = <0x0 0xff3b0000 0x0 0x1000>, /* 0: HCI standard */