From patchwork Mon May 22 11:58:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 9740027 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AB6C56034C for ; Mon, 22 May 2017 12:00:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 874EB28641 for ; Mon, 22 May 2017 12:00:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7ACB7286F2; Mon, 22 May 2017 12:00:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1C14028641 for ; Mon, 22 May 2017 12:00:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759282AbdEVMAH (ORCPT ); Mon, 22 May 2017 08:00:07 -0400 Received: from mail-pf0-f178.google.com ([209.85.192.178]:33732 "EHLO mail-pf0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759325AbdEVMAA (ORCPT ); Mon, 22 May 2017 08:00:00 -0400 Received: by mail-pf0-f178.google.com with SMTP id e193so80451938pfh.0 for ; Mon, 22 May 2017 05:00:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wowiYIj9ckW8JX7EB61kV1QYYejtnTAvF8jgDFfnT0w=; b=LZH4FpSMluTjrvpn7UFq6CVB+BFqvdTGo1PXNQeHbCrfr+wE/EC1edcDBvOrF9vJcl EH/6EWieLXO5sXUSNqrzZJqNepI4carVQfBQC7KcU03ekoIfk3eXsPwtqJugwrSVIWKd cKqja9Nke/eBQQAxJfCXDSt49ivfh9/618tDs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wowiYIj9ckW8JX7EB61kV1QYYejtnTAvF8jgDFfnT0w=; b=oKPQNrbQEdTqjvOmGBsPISw/TNiplCNR2GCUTEMMvar3xLzHlDJK04UyNE5XQrUOQd wbUibHiXeK89OitXhrFQdA1ZbGSHL3WbjecvGswN/nQ/NfF3CKw0T4WxVxQwb4suMXX6 wqPww1aamu8buP99YSKbbySUQRvm2+AJ9R1L4rwwll+pyUbcOUwOgokI88WzpaLPOE/o /40eQObOykWBx2VOSDElh+F2iuYPm/GrSENOKcdqR5hjTTpvhO5k6pQB73N52iTYzAeO DOOlq88yixbbHGcpiHbmBmqTV620/7VjIbyB37ZEogEJeb6PL9KaOzvpcdScH1tNXYNk o2Rw== X-Gm-Message-State: AODbwcD0eayD0vEu7uZdZY6pEK00pBQON5AgO8rJm83ELf+ir+Dm5SCX bP/lmg/sMLp2GDIu X-Received: by 10.98.211.87 with SMTP id q84mr25399971pfg.126.1495454400051; Mon, 22 May 2017 05:00:00 -0700 (PDT) Received: from anup-HP-Compaq-8100-Elite-CMT-PC.dhcp.avagotech.net ([192.19.237.250]) by smtp.gmail.com with ESMTPSA id m24sm28673653pfi.129.2017.05.22.04.59.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 22 May 2017 04:59:59 -0700 (PDT) From: Anup Patel To: Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: Catalin Marinas , Will Deacon , Ray Jui , Scott Branden , Jon Mason , Florian Fainelli , Oza Pawandeep , Srinath Mannam , Pramod Kumar , Sandeep Tripathy , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, bcm-kernel-feedback-list@broadcom.com, Anup Patel Subject: [PATCH v4 11/11] arm64: dts: Add PWM and SDHCI DT nodes for Stingray SOC Date: Mon, 22 May 2017 17:28:27 +0530 Message-Id: <1495454307-23464-12-git-send-email-anup.patel@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495454307-23464-1-git-send-email-anup.patel@broadcom.com> References: <1495454307-23464-1-git-send-email-anup.patel@broadcom.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinath Mannam The Stingray SoC has two instances of SDHCI controller and one instance of iProc PWM. Let's enable above mentioned devices in Stingray DT. Signed-off-by: Srinath Mannam Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- .../boot/dts/broadcom/stingray/bcm958742-base.dtsi | 39 ++++++++++++++++++++++ .../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 28 ++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi index ff59a26..5dca7d1 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi @@ -43,6 +43,28 @@ serial2 = &uart2; serial3 = &uart3; }; + + sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl { + compatible = "regulator-gpio"; + regulator-name = "sdio0_vddo_ctrl_reg"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pca9505 18 0>; + states = <3300000 0x0 + 1800000 0x1>; + }; + + sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl { + compatible = "regulator-gpio"; + regulator-name = "sdio1_vddo_ctrl_reg"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pca9505 19 0>; + states = <3300000 0x0 + 1800000 0x1>; + }; }; &memory { /* Default DRAM banks */ @@ -54,6 +76,10 @@ status = "okay"; }; +&pwm { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -90,3 +116,16 @@ #size-cells = <1>; }; }; + +&sdio0 { + vqmmc-supply = <&sdio0_vddo_ctrl_reg>; + non-removable; + full-pwr-cycle; + status = "okay"; +}; + +&sdio1 { + vqmmc-supply = <&sdio1_vddo_ctrl_reg>; + full-pwr-cycle; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 642d42c..44ed73c 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -269,6 +269,14 @@ #include "stingray-pinctrl.dtsi" + pwm: pwm@68910000{ + compatible = "brcm,iproc-pwm"; + reg = <0x00010000 0x1000>; + clocks = <&crmu_ref25m>; + #pwm-cells = <3>; + status = "disabled"; + }; + i2c0: i2c@689b0000 { compatible = "brcm,iproc-i2c"; reg = <0x000b0000 0x100>; @@ -428,5 +436,25 @@ brcm,nand-has-wp; status = "disabled"; }; + + sdio0: sdhci@68cf1000 { + compatible = "brcm,sdhci-iproc"; + reg = <0x003f1000 0x100>; + interrupts = ; + bus-width = <8>; + clocks = <&sdio0_clk>; + iommus = <&smmu 0x6002 0x0000>; + status = "disabled"; + }; + + sdio1: sdhci@68cf2000 { + compatible = "brcm,sdhci-iproc"; + reg = <0x003f2000 0x100>; + interrupts = ; + bus-width = <8>; + clocks = <&sdio1_clk>; + iommus = <&smmu 0x6003 0x0000>; + status = "disabled"; + }; }; };