From patchwork Wed May 24 09:43:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 9745613 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DF7EA60209 for ; Wed, 24 May 2017 09:45:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C78E228932 for ; Wed, 24 May 2017 09:45:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BBC1128938; Wed, 24 May 2017 09:45:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 384DE2893C for ; Wed, 24 May 2017 09:44:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936738AbdEXJor (ORCPT ); Wed, 24 May 2017 05:44:47 -0400 Received: from mail-wm0-f41.google.com ([74.125.82.41]:36963 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S938469AbdEXJnv (ORCPT ); Wed, 24 May 2017 05:43:51 -0400 Received: by mail-wm0-f41.google.com with SMTP id d127so61035896wmf.0 for ; Wed, 24 May 2017 02:43:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=xKy+Nn2TQhTFUrYWhgOWp0xJEf+97aBwr7hSuc25bAQ=; b=Rt+KwiJghgUhTRACyJeUt9fo2PVMyw/p3QDYtkdwRA121o0SjQ1/222TVFVKLBklxj Fw6K7Xqme/cngqi8U8C4fOyxH49GFofYD24ezP5Ryhst7yNtccYlfET3xDj4YwbUjmoX zZkgZ6HoO6pHcoGiivFmnPvdfRX7id4FcXwuZbrou733IQVvCpwaFjGyszYUOQjZZ6cR VHTzv0SXDfpGMXr7eO/9sH0wpKe3ZOEXGp/8ziHsg+beYw9PhMVTgdPCD/wrJ8BkWqN3 V6Y0axzRbCkJ1D6CbgD5Qme7yFZUrYFU41UUTDymf6GeG3jn/JV2lXC3EDHdscylb4Mx ipZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=xKy+Nn2TQhTFUrYWhgOWp0xJEf+97aBwr7hSuc25bAQ=; b=YqxQmktJL51JcA7R0mvRTfVcPi+VkPM0S2PqqFLVRS63i1Zi0RT/+f7OBGwXRA4LaG qPp34WGJf/wr5fc2Rxsuc8RvzHlyyfwf6glqzX94FW1fmyihmLUrXiMfZ5XmpbzzbVPf 049eUNL55rO9fufaOeNzhxGq3TAjeI3uTnh8UV6F3OS1iILCxFnu3r8mf8VEJst1NjzD x1dftbK6Hz2lYLa3uGsaMv1sFRJ8QrCLGXxE9C/z1M5GmzmFr/UPDmSvUSsxbICa7g/2 MwXGi6W5ThPW781jU1oTk0AozqqAVqXkdW2VI/YWoAUQispUq0wdFShUPejm8jEl2hC0 IJnQ== X-Gm-Message-State: AODbwcCqX961fHa9djuDRZBQ+Ua99mtqDph52jW4Ivjz/V7KxDrXCig9 Nj6KjhhPj/OEtVbR X-Received: by 10.28.184.216 with SMTP id i207mr5824057wmf.31.1495619028442; Wed, 24 May 2017 02:43:48 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id q203sm3223698wme.0.2017.05.24.02.43.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 May 2017 02:43:47 -0700 (PDT) From: Neil Armstrong To: narmstrong@baylibre.com, jbrunet@baylibre.com Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk: meson-gxbb: Add EE 32K Clock for CEC Date: Wed, 24 May 2017 11:43:45 +0200 Message-Id: <1495619025-1958-1-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Amlogic GX SoCs, there is two CEC controllers : - An Amlogic CEC custom in the AO domain - The Synopsys HDMI-TX Controller in the EE domain Each of these controllers needs a 32.768KHz clock, but there is two paths : - In the EE domain, the "32k_clk" this patchs is adding - In the AO domain, with a more complex dual divider more precise setup The AO 32K clock support will be pushed later in the corresponding gxbb-aoclk driver when the AE CEC driver is ready. The EE 32k_clk must be pushed earlier since mainline support for CEC in the Synopsys HDMI-TX controller is nearby. Signed-off-by: Neil Armstrong --- drivers/clk/meson/gxbb.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/gxbb.h | 5 ++++- 2 files changed, 58 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index ad5f027..4b7d85a 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -951,6 +951,51 @@ struct pll_params_table gxl_gp0_params_table[] = { }, }; +static struct clk_divider gxbb_32k_clk_div = { + .reg = (void *)HHI_32K_CLK_CNTL, + .shift = 0, + .width = 14, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "32k_clk_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "32k_clk_sel" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, + }, +}; + +static struct clk_gate gxbb_32k_clk = { + .reg = (void *)HHI_32K_CLK_CNTL, + .bit_idx = 15, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "32k_clk", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "32k_clk_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const char *gxbb_32k_clk_parent_names[] = { + "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5" +}; + +static struct clk_mux gxbb_32k_clk_sel = { + .reg = (void *)HHI_32K_CLK_CNTL, + .mask = 0x3, + .shift = 16, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "32k_clk_sel", + .ops = &clk_mux_ops, + .parent_names = gxbb_32k_clk_parent_names, + .num_parents = 4, + .flags = CLK_SET_RATE_PARENT, + }, +}; + /* Everything Else (EE) domain gates */ static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); @@ -1158,6 +1203,9 @@ struct pll_params_table gxl_gp0_params_table[] = { [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, [CLKID_CTS_I958] = &gxbb_cts_i958.hw, + [CLKID_32K_CLK] = &gxbb_32k_clk.hw, + [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, + [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, }, .num = NR_CLKS, }; @@ -1278,6 +1326,9 @@ struct pll_params_table gxl_gp0_params_table[] = { [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, [CLKID_CTS_I958] = &gxbb_cts_i958.hw, + [CLKID_32K_CLK] = &gxbb_32k_clk.hw, + [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, + [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, }, .num = NR_CLKS, }; @@ -1392,6 +1443,7 @@ struct pll_params_table gxl_gp0_params_table[] = { &gxbb_mali_1, &gxbb_cts_amclk, &gxbb_cts_mclk_i958, + &gxbb_32k_clk, }; static struct clk_mux *const gxbb_clk_muxes[] = { @@ -1403,6 +1455,7 @@ struct pll_params_table gxl_gp0_params_table[] = { &gxbb_cts_amclk_sel, &gxbb_cts_mclk_i958_sel, &gxbb_cts_i958, + &gxbb_32k_clk_sel, }; static struct clk_divider *const gxbb_clk_dividers[] = { @@ -1411,6 +1464,7 @@ struct pll_params_table gxl_gp0_params_table[] = { &gxbb_mali_0_div, &gxbb_mali_1_div, &gxbb_cts_mclk_i958_div, + &gxbb_32k_clk_div, }; static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index 93b8f07..de5fad0 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -284,8 +284,11 @@ #define CLKID_CTS_MCLK_I958_SEL 111 #define CLKID_CTS_MCLK_I958_DIV 112 #define CLKID_CTS_I958 113 +#define CLKID_32K_CLK 114 +#define CLKID_32K_CLK_SEL 115 +#define CLKID_32K_CLK_DIV 116 -#define NR_CLKS 114 +#define NR_CLKS 117 /* include the CLKIDs that have been made part of the stable DT binding */ #include