From patchwork Tue Jun 20 08:56:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Binbin Zhou X-Patchwork-Id: 9798765 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EF5AE60329 for ; Tue, 20 Jun 2017 08:57:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E486B28456 for ; Tue, 20 Jun 2017 08:57:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D90082846D; Tue, 20 Jun 2017 08:57:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3C8B928477 for ; Tue, 20 Jun 2017 08:57:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752462AbdFTI5Z (ORCPT ); Tue, 20 Jun 2017 04:57:25 -0400 Received: from smtpbg328.qq.com ([14.17.43.160]:36577 "EHLO smtpbg328.qq.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752420AbdFTI5V (ORCPT ); Tue, 20 Jun 2017 04:57:21 -0400 X-QQ-mid: bizesmtp2t1497948999t068w2x8a Received: from software.domain.org (unknown [222.92.8.142]) by esmtp4.qq.com (ESMTP) with id ; Tue, 20 Jun 2017 16:56:38 +0800 (CST) X-QQ-SSF: 01100000008000F0FI91000A0000000 X-QQ-FEAT: Dh0h8S2M+VbEmMAkiLBQrZGTn3nQEjWDs2KOrMsiRl8CracLHI1YP5A2CMVkk rzI31geup4QWwyOerWReiZNraMw5TneoBQMPzTboCkC4ZTdzb02STRoOJBx9e8DczsG4nJo k2i30Um4c1rfKA0htKtmUUQ4LIe4j6axKJox2RbJkdvNFpSW4EMsXvQOSD6xDDjLTwmZl8W oHNs1Lp4lj0Mwi5pXvxq7u2PCr+aCIfnHKmNky46upXHX+vBZHiPdyfzLVhzlHHaXIbau28 4S4ZX/LNNulWpoKA18BeqRO5rckAArs/IrcMmilk7caDU+5JpjwH5RZSE= X-QQ-GoodBg: 0 From: Binbin Zhou To: Ralf Baechle , James Hogan Cc: John Crispin , "Steven J . Hill" , Aurelien Jarno , Fuxin Zhang , Zhangjin Wu , Kelvin Cheung , Yang Ling , =?UTF-8?q?=E8=B0=A2=E8=87=B4=E9=82=A6?= , Stephen Boyd , Michael Turquette , linux-mips@linux-mips.org, linux-clk@vger.kernel.org, Binbin Zhou , HuaCai Chen Subject: [PATCH v8 1/9] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1C Date: Tue, 20 Jun 2017 16:56:59 +0800 Message-Id: <1497949027-10988-2-git-send-email-zhoubb@lemote.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1497949027-10988-1-git-send-email-zhoubb@lemote.com> References: <1497949027-10988-1-git-send-email-zhoubb@lemote.com> X-QQ-SENDSIZE: 520 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Loongson-1 series CPUs(1A/1B/1C) share the same PRID macro. Signed-off-by: Binbin Zhou Signed-off-by: HuaCai Chen --- arch/mips/include/asm/cpu.h | 3 +-- arch/mips/kernel/cpu-probe.c | 4 +++- arch/mips/loongson32/common/setup.c | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 3069359..71c624d 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -240,8 +240,7 @@ #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 #define PRID_REV_34K_V1_0_2 0x0022 -#define PRID_REV_LOONGSON1B 0x0020 -#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */ +#define PRID_REV_LOONGSON1ABC 0x0020 #define PRID_REV_LOONGSON2E 0x0002 #define PRID_REV_LOONGSON2F 0x0003 #define PRID_REV_LOONGSON3A_R1 0x0005 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 353ade2..25f729c 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1513,8 +1513,10 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_LOONGSON1; switch (c->processor_id & PRID_REV_MASK) { - case PRID_REV_LOONGSON1B: + case PRID_REV_LOONGSON1ABC: +#ifdef CONFIG_CPU_LOONGSON1B __cpu_name[cpu] = "Loongson 1B"; +#endif break; } diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/common/setup.c index 1640744..c8e8b3e 100644 --- a/arch/mips/loongson32/common/setup.c +++ b/arch/mips/loongson32/common/setup.c @@ -21,7 +21,7 @@ const char *get_system_type(void) unsigned int processor_id = (¤t_cpu_data)->processor_id; switch (processor_id & PRID_REV_MASK) { - case PRID_REV_LOONGSON1B: + case PRID_REV_LOONGSON1ABC: #if defined(CONFIG_LOONGSON1_LS1B) return "LOONGSON LS1B"; #elif defined(CONFIG_LOONGSON1_LS1C)