From patchwork Thu Jul 6 09:37:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Gautam X-Patchwork-Id: 9827827 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 87ED6604D9 for ; Thu, 6 Jul 2017 09:38:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 68B2A2847B for ; Thu, 6 Jul 2017 09:38:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5BB1D2854F; Thu, 6 Jul 2017 09:38:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C247A283C9 for ; Thu, 6 Jul 2017 09:38:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752301AbdGFJiP (ORCPT ); Thu, 6 Jul 2017 05:38:15 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:35698 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750778AbdGFJiM (ORCPT ); Thu, 6 Jul 2017 05:38:12 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id C90A16121B; Thu, 6 Jul 2017 09:37:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1499333886; bh=zwmERIm0F3l6510MWJIUy8swaQzKUc8ahCV2BnleqzE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JS71x+kmP9GGIjZWiQqNxinr7IQIPAbtwOVrt2TWDIZA9BppQOldg5d1BNKkaO1mh 5nlD5oqMzUHM70nkuLgff3uJ9Y+soeyFqsCr1taWvy6+MDBvzqT3y/VgWjr2X41r/j 7fx+UzAIxNgxFxfoyZsjSzpimAYwLhPH+gksMb+s= Received: from blr-ubuntu-41.ap.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: vivek.gautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5CC0A60AD7; Thu, 6 Jul 2017 09:37:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1499333871; bh=zwmERIm0F3l6510MWJIUy8swaQzKUc8ahCV2BnleqzE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DgktjKjnxo8vWAbkeNXcl+MBLtAYgStHOm7xxO2IzMdKz1pAuj4ztfCtBY8NSXEDX xIITLok544XNFShN5D+QbzZwx3ycsKGsVkRb6Kx7XQKMhmlPaBrM+2skSLawpKk3t0 385RGXq6txuP39phHYuleXo0lLvyORr4l672/m5w= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5CC0A60AD7 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org From: Vivek Gautam To: joro@8bytes.org, robin.murphy@arm.com, robh+dt@kernel.org, mark.rutland@arm.com, will.deacon@arm.com, m.szyprowski@samsung.com, sboyd@codeaurora.org, robdclark@gmail.com, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, sricharan@codeaurora.org, stanimir.varbanov@linaro.org, architt@codeaurora.org, vivek.gautam@codeaurora.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH V4 6/6] iommu/arm-smmu: Add support for qcom, msm8996-smmu-v2 clocks Date: Thu, 6 Jul 2017 15:07:05 +0530 Message-Id: <1499333825-7658-7-git-send-email-vivek.gautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1499333825-7658-1-git-send-email-vivek.gautam@codeaurora.org> References: <1499333825-7658-1-git-send-email-vivek.gautam@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP qcom,msm8996-smmu-v2 is an arm,smmu-v2 implementation with specific clock and power requirements. This smmu core is used with multiple masters on msm8996, viz. mdss, video, etc. Add bindings for the same. Signed-off-by: Vivek Gautam --- Documentation/devicetree/bindings/iommu/arm,smmu.txt | 18 ++++++++++++++++++ drivers/iommu/arm-smmu.c | 13 +++++++++++++ 2 files changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 00331752d355..5d8e79775fae 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -17,6 +17,7 @@ conditions. "arm,mmu-401" "arm,mmu-500" "cavium,smmu-v2" + "qcom,msm8996-smmu-v2" depending on the particular implementation and/or the version of the architecture implemented. @@ -74,11 +75,16 @@ conditions. - clock-names: Should be "tcu" and "iface" for "arm,mmu-400", "arm,mmu-401" and "arm,mmu-500" + Should be "bus", and "iface" for "qcom,msm8996-smmu-v2" + implementation. + "tcu" clock is required for smmu's register access using the programming interface and ptw for downstream bus access. This clock is also used for access to the TBU connected to the master locally. Sometimes however, TBU is clocked along with the master. + "bus" clock for "qcom,msm8996-smmu-v2" is requierd for downstream + bus access and for the smmu ptw. "iface" clock is required to access the TCU's programming interface, apart from the "tcu" clock. @@ -161,3 +167,15 @@ conditions. iommu-map = <0 &smmu3 0 0x400>; ... }; + + /* Qcom's arm,smmu-v2 implementation for msm8996 */ + smmu4: iommu { + compatible = "qcom,msm8996-smmu-v2"; + ... + #iommu-cells = <1>; + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc SMMU_MDP_AXI_CLK>, + <&mmcc SMMU_MDP_AHB_CLK>; + clock-names = "bus", "iface"; + }; diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 7bb09280fa11..fe8e7fd61282 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -110,6 +110,7 @@ enum arm_smmu_implementation { GENERIC_SMMU, ARM_MMU500, CAVIUM_SMMUV2, + QCOM_MSM8996_SMMUV2, }; /* Until ACPICA headers cover IORT rev. C */ @@ -1960,6 +1961,17 @@ struct arm_smmu_match_data { .num_clks = ARRAY_SIZE(arm_mmu500_clks), }; +static const char * const qcom_msm8996_smmuv2_clks[] = { + "bus", "iface", +}; + +static const struct arm_smmu_match_data qcom_msm8996_smmuv2 = { + .version = ARM_SMMU_V2, + .model = QCOM_MSM8996_SMMUV2, + .clks = qcom_msm8996_smmuv2_clks, + .num_clks = ARRAY_SIZE(qcom_msm8996_smmuv2_clks), +}; + static const struct of_device_id arm_smmu_of_match[] = { { .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 }, { .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 }, @@ -1967,6 +1979,7 @@ struct arm_smmu_match_data { { .compatible = "arm,mmu-401", .data = &arm_mmu401 }, { .compatible = "arm,mmu-500", .data = &arm_mmu500 }, { .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 }, + { .compatible = "qcom,msm8996-smmu-v2", .data = &qcom_msm8996_smmuv2 }, { }, }; MODULE_DEVICE_TABLE(of, arm_smmu_of_match);