From patchwork Thu Jul 20 04:48:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 9853761 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7C90E60392 for ; Thu, 20 Jul 2017 04:48:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 65E9828737 for ; Thu, 20 Jul 2017 04:48:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5AEE828748; Thu, 20 Jul 2017 04:48:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DCC2528737 for ; Thu, 20 Jul 2017 04:48:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933246AbdGTEsy (ORCPT ); Thu, 20 Jul 2017 00:48:54 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:49930 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932745AbdGTEsx (ORCPT ); Thu, 20 Jul 2017 00:48:53 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 689936121D; Thu, 20 Jul 2017 04:48:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1500526133; bh=PClU7nUeIPdS+WPkeiWo5TImt3uvhOBQVOg2JRm1Ri8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V74P7nSHtYjIV0X77TzcMS7pd+heix01b+e6CE3Mqpz7tSmL6iDatZ8t21ixNiEf6 hTFWvszmWOyKanFRTI30ahddqVyVyR0Aubrxi1LHRAIuyRgAZKwF0vXzw9iJvp7Jkq lqV7j8z7b5QMzD29sY+mVNZ0eIoeREhKiiI4nwZk= Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 290F5611C8; Thu, 20 Jul 2017 04:48:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1500526132; bh=PClU7nUeIPdS+WPkeiWo5TImt3uvhOBQVOg2JRm1Ri8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mfuwCv10d5vlKflAudBSs64a4j1HPklEE8JatVkc3YjuJsy15AWanyS7VFx5Q3zdO 3EI6+RsLkvcTwSLt1glOHK7rfDqbhgy4z6HESuClbJJRwHmLVm91g3BCxU9MbBoPdR 4JtoTYsEKP48Yj5d0EIKVYjBkhJhH2BKHvugxq/s= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 290F5611C8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stanimir.varbanov@linaro.org, vivek.gautam@codeaurora.org, Rajendra Nayak Subject: [PATCH v2 3/5] clk: qcom: gdsc: Add support to control associated clks Date: Thu, 20 Jul 2017 10:18:17 +0530 Message-Id: <1500526099-9935-4-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500526099-9935-1-git-send-email-rnayak@codeaurora.org> References: <1500526099-9935-1-git-send-email-rnayak@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The devices within a gdsc power domain, quite often have additional clocks to be turned on/off along with the power domain itself. Add support for this by specifying a list of clk_hw pointers per gdsc which would be the clocks turned on/off along with the powerdomain on/off callbacks. Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/gdsc.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++-- drivers/clk/qcom/gdsc.h | 8 +++++++ 2 files changed, 66 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index a4f3580..7e7c051 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -12,6 +12,8 @@ */ #include +#include +#include #include #include #include @@ -21,6 +23,7 @@ #include #include #include +#include "common.h" #include "gdsc.h" #define PWR_ON_MASK BIT(31) @@ -166,6 +169,29 @@ static inline void gdsc_assert_clamp_io(struct gdsc *sc) GMEM_CLAMP_IO_MASK, 1); } +static inline int gdsc_clk_enable(struct gdsc *sc) +{ + int i, ret; + + for (i = 0; i < sc->clk_count; i++) { + ret = clk_prepare_enable(sc->clks[i]); + if (ret) { + for (i--; i >= 0; i--) + clk_disable_unprepare(sc->clks[i]); + return ret; + } + } + return 0; +} + +static inline void gdsc_clk_disable(struct gdsc *sc) +{ + int i; + + for (i = 0; i < sc->clk_count; i++) + clk_disable_unprepare(sc->clks[i]); +} + static int gdsc_enable(struct generic_pm_domain *domain) { struct gdsc *sc = domain_to_gdsc(domain); @@ -193,6 +219,10 @@ static int gdsc_enable(struct generic_pm_domain *domain) */ udelay(1); + ret = gdsc_clk_enable(sc); + if (ret) + return ret; + /* Turn on HW trigger mode if supported */ if (sc->flags & HW_CTRL) { ret = gdsc_hwctrl(sc, true); @@ -241,6 +271,8 @@ static int gdsc_disable(struct generic_pm_domain *domain) return ret; } + gdsc_clk_disable(sc); + if (sc->pwrsts & PWRSTS_OFF) gdsc_clear_mem_on(sc); @@ -254,7 +286,27 @@ static int gdsc_disable(struct generic_pm_domain *domain) return 0; } -static int gdsc_init(struct gdsc *sc) +static inline int gdsc_clk_get(struct device *dev, struct gdsc *sc) +{ + if (sc->clk_count) { + int i; + + sc->clks = devm_kcalloc(dev, sc->clk_count, sizeof(*sc->clks), + GFP_KERNEL); + if (!sc->clks) + return -ENOMEM; + + for (i = 0; i < sc->clk_count; i++) { + sc->clks[i] = devm_clk_hw_get_clk(dev, sc->clk_hws[i], + NULL); + if (IS_ERR(sc->clks[i])) + return PTR_ERR(sc->clks[i]); + } + } + return 0; +} + +static int gdsc_init(struct device *dev, struct gdsc *sc) { u32 mask, val; int on, ret; @@ -284,6 +336,10 @@ static int gdsc_init(struct gdsc *sc) if (on < 0) return on; + ret = gdsc_clk_get(dev, sc); + if (ret) + return ret; + /* * Votable GDSCs can be ON due to Vote from other masters. * If a Votable GDSC is ON, make sure we have a Vote. @@ -327,7 +383,7 @@ int gdsc_register(struct gdsc_desc *desc, continue; scs[i]->regmap = regmap; scs[i]->rcdev = rcdev; - ret = gdsc_init(scs[i]); + ret = gdsc_init(dev, scs[i]); if (ret) return ret; data->domains[i] = &scs[i]->pd; diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 3964834..a7fd51b 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -17,6 +17,8 @@ #include #include +struct clk; +struct clk_hw; struct regmap; struct reset_controller_dev; @@ -32,6 +34,9 @@ * @resets: ids of resets associated with this gdsc * @reset_count: number of @resets * @rcdev: reset controller + * @clk_count: number of gdsc clocks + * @clks: clk pointers for gdsc clocks + * @clk_hws: clk_hw pointers for gdsc clocks */ struct gdsc { struct generic_pm_domain pd; @@ -56,6 +61,9 @@ struct gdsc { struct reset_controller_dev *rcdev; unsigned int *resets; unsigned int reset_count; + unsigned int clk_count; + struct clk **clks; + struct clk_hw *clk_hws[]; }; struct gdsc_desc {