From patchwork Tue Jul 25 07:16:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhangqing X-Patchwork-Id: 9861273 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3ED06602B1 for ; Tue, 25 Jul 2017 07:12:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 302232832D for ; Tue, 25 Jul 2017 07:12:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 24D9F285FE; Tue, 25 Jul 2017 07:12:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8A4FF2832D for ; Tue, 25 Jul 2017 07:12:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750814AbdGYHMi (ORCPT ); Tue, 25 Jul 2017 03:12:38 -0400 Received: from regular1.263xmail.com ([211.150.99.133]:41790 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750780AbdGYHMh (ORCPT ); Tue, 25 Jul 2017 03:12:37 -0400 Received: from zhangqing?rock-chips.com (unknown [192.168.167.130]) by regular1.263xmail.com (Postfix) with ESMTP id D2E2690E3; Tue, 25 Jul 2017 15:12:30 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 9EF963B0; Tue, 25 Jul 2017 15:12:28 +0800 (CST) X-RL-SENDER: zhangqing@rock-chips.com X-FST-TO: mturquette@baylibre.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zhangqing@rock-chips.com X-UNIQUE-TAG: <4938d23b587ee9440204e8136b02ebdf> X-ATTACHMENT-NUM: 0 X-SENDER: zhangqing@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 22274RE7UK; Tue, 25 Jul 2017 15:12:31 +0800 (CST) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@codeaurora.org, heiko@sntech.de Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com, cl@rock-chips.com, Elaine Zhang Subject: [PATCH v1] clk: rockchip: rk3128: modify rk3128 clk driver to support rk3126 Date: Tue, 25 Jul 2017 15:16:36 +0800 Message-Id: <1500966996-5660-1-git-send-email-zhangqing@rock-chips.com> X-Mailer: git-send-email 1.9.1 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP rk3128 and rk3126 have some gate registers describe differences. So need to make some distinctions. Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3128.c | 59 +++++++++++++++++++++++++++++++--- include/dt-bindings/clock/rk3128-cru.h | 3 ++ 2 files changed, 57 insertions(+), 5 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c index e243f2eae68f..0039b8940900 100644 --- a/drivers/clk/rockchip/clk-rk3128.c +++ b/drivers/clk/rockchip/clk-rk3128.c @@ -459,9 +459,8 @@ enum rk3128_plls { RK2928_CLKSEL_CON(2), 14, 2, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(10), 15, GFLAGS), - COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0, - RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS, - RK2928_CLKGATE_CON(3), 15, GFLAGS), + COMPOSITE_NOGATE(0, "sclk_sfc_src", mux_sclk_sfc_src_p, 0, + RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS), COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "cpll", 0, RK2928_CLKSEL_CON(29), 8, 6, DFLAGS, @@ -495,7 +494,6 @@ enum rk3128_plls { GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS), GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS), GATE(0, "aclk_cpu_to_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS), - GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS), @@ -541,7 +539,6 @@ enum rk3128_plls { GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS), GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), - GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS), GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS), GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS), GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), @@ -574,6 +571,7 @@ static void __init rk3128_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk *clk; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -593,6 +591,57 @@ static void __init rk3128_clk_init(struct device_node *np) RK3128_GRF_SOC_STATUS0); rockchip_clk_register_branches(ctx, rk3128_clk_branches, ARRAY_SIZE(rk3128_clk_branches)); + + if (of_machine_is_compatible("rockchip,rk3128")) { + clk = clk_register_gate(NULL, "sclk_sfc", "sclk_sfc_src", 0, + ctx->reg_base + RK2928_CLKGATE_CON(3), 15, GFLAGS, &ctx->lock); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock sclk_sfc: %ld\n", + __func__, PTR_ERR(clk)); + else + rockchip_clk_add_lookup(ctx, clk, SCLK_SFC); + + clk = clk_register_gate(NULL, "hclk_gps", "aclk_peri", 0, + ctx->reg_base + RK2928_CLKGATE_CON(3), 14, GFLAGS, &ctx->lock); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock hclk_gps: %ld\n", + __func__, PTR_ERR(clk)); + else + rockchip_clk_add_lookup(ctx, clk, HCLK_GPS); + + clk = clk_register_gate(NULL, "pclk_hdmi", "pclk_cpu", 0, + ctx->reg_base + RK2928_CLKGATE_CON(3), 8, GFLAGS, &ctx->lock); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock pclk_hdmi: %ld\n", + __func__, PTR_ERR(clk)); + else + rockchip_clk_add_lookup(ctx, clk, PCLK_HDMI); + } else { + clk = clk_register_gate(NULL, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, + ctx->reg_base + RK2928_CLKGATE_CON(3), 15, GFLAGS, &ctx->lock); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock pclk_stimer: %ld\n", + __func__, PTR_ERR(clk)); + else + rockchip_clk_add_lookup(ctx, clk, PCLK_STIMER); + + clk = clk_register_gate(NULL, "pclk_s_efuse", "pclk_cpu", CLK_IGNORE_UNUSED, + ctx->reg_base + RK2928_CLKGATE_CON(3), 14, GFLAGS, &ctx->lock); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock pclk_s_efuse: %ld\n", + __func__, PTR_ERR(clk)); + else + rockchip_clk_add_lookup(ctx, clk, PCLK_S_EFUSE); + + clk = clk_register_gate(NULL, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, + ctx->reg_base + RK2928_CLKGATE_CON(3), 8, GFLAGS, &ctx->lock); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock pclk_sgrf: %ld\n", + __func__, PTR_ERR(clk)); + else + rockchip_clk_add_lookup(ctx, clk, PCLK_SGRF); + } + rockchip_clk_protect_critical(rk3128_critical_clocks, ARRAY_SIZE(rk3128_critical_clocks)); diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h index 92894f4306cf..0451c9c42375 100644 --- a/include/dt-bindings/clock/rk3128-cru.h +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -125,6 +125,9 @@ #define PCLK_GMAC 367 #define PCLK_PMU_PRE 368 #define PCLK_SIM_CARD 369 +#define PCLK_STIMER 370 +#define PCLK_S_EFUSE 371 +#define PCLK_SGRF 372 /* hclk gates */ #define HCLK_SPDIF 440