From patchwork Tue Jul 25 10:34:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 9861737 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A3A90601A1 for ; Tue, 25 Jul 2017 10:43:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 529D823794 for ; Tue, 25 Jul 2017 10:43:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 43ED32862C; Tue, 25 Jul 2017 10:43:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CEDBA2832D for ; Tue, 25 Jul 2017 10:43:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751817AbdGYKkd (ORCPT ); Tue, 25 Jul 2017 06:40:33 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:8756 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751815AbdGYKjp (ORCPT ); Tue, 25 Jul 2017 06:39:45 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 25 Jul 2017 03:39:42 -0700 Received: from HQMAIL108.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 25 Jul 2017 03:39:45 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 25 Jul 2017 03:39:45 -0700 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Tue, 25 Jul 2017 10:39:45 +0000 Received: from tbergstrom-lnx.Nvidia.com (10.21.24.170) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Tue, 25 Jul 2017 10:39:41 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id 7DF4DF80591; Tue, 25 Jul 2017 13:34:34 +0300 (EEST) From: Peter De Schrijver To: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , "Stephen Boyd" , Thierry Reding , Jonathan Hunter , , , CC: Alex Frid Subject: [PATCH 13/14] clk: tegra: Correct Tegra210 UTMIPLL poweron delay Date: Tue, 25 Jul 2017 13:34:14 +0300 Message-ID: <1500978856-5981-14-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500978856-5981-1-git-send-email-pdeschrijver@nvidia.com> References: <1500978856-5981-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Alex Frid Increased Tegra210 UTMIPLL power on delay to 20us (spec maximum is 15us). Also remove a few empty lines to make it more clear the ACTIVE_DLY_COUNT and ENABLE_DLY_COUNT fields. Signed-off-by: Alex Frid Reviewed-by: Peter De Schrijver Reviewed-by: Jon Mayo --- drivers/clk/tegra/clk-tegra210.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 4fa7ab3..fd04b0e 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2472,15 +2472,14 @@ static void tegra210_utmi_param_configure(void) reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); - reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count); writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); /* Program UTMIP PLL delay and oscillator frequency counts */ reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); - reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); + reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count); @@ -2496,7 +2495,8 @@ static void tegra210_utmi_param_configure(void) reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); - udelay(1); + + udelay(20); /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */ reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);