From patchwork Tue Jul 25 19:17:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergej Sawazki X-Patchwork-Id: 9863111 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0431C6038C for ; Tue, 25 Jul 2017 19:52:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F177F286CC for ; Tue, 25 Jul 2017 19:52:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E61A0286E1; Tue, 25 Jul 2017 19:52:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 000CD286CC for ; Tue, 25 Jul 2017 19:52:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752162AbdGYTvo (ORCPT ); Tue, 25 Jul 2017 15:51:44 -0400 Received: from s62.goserver.host ([37.17.224.62]:56382 "EHLO s62.goserver.host" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753816AbdGYTYi (ORCPT ); Tue, 25 Jul 2017 15:24:38 -0400 X-Greylist: delayed 348 seconds by postgrey-1.27 at vger.kernel.org; Tue, 25 Jul 2017 15:24:37 EDT Received: from duke.fritz.box (p5B23A86E.dip0.t-ipconnect.de [91.35.168.110]) by s62.goserver.host (Postfix) with ESMTPSA id 970B3BD00770; Tue, 25 Jul 2017 21:18:46 +0200 (CEST) From: Sergej Sawazki To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-clk@vger.kernel.org, ce3a@gmx.de, Sergej Sawazki , Sebastian Hesselbarth , Rabeeh Khoury Subject: [PATCH] clk: si5351: Apply PLL soft reset before enabling the outputs Date: Tue, 25 Jul 2017 21:17:41 +0200 Message-Id: <1501010261-7130-1-git-send-email-sergej@taudac.com> X-Mailer: git-send-email 2.7.4 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The "Si5351A/B/C Data Sheet" states to apply a PLLA and PLLB soft reset before enabling the outputs [1]. This is required to get a deterministic phase relationship between the output clocks. Without the PLL reset, the phase offset beween the clocks is unpredictable. References: [1] https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf Figure 12 ("I2C Programming Procedure") Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Signed-off-by: Sergej Sawazki --- drivers/clk/clk-si5351.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 255d0fe..6cca425 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -905,6 +905,15 @@ static int si5351_clkout_prepare(struct clk_hw *hw) si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, SI5351_CLK_POWERDOWN, 0); + + /* + * Reset the PLLs before enabling the outputs to get a deterministic + * phase relationship between the output clocks. Otherwise, the phase + * offset beween the clocks is unpredictable. + */ + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, + SI5351_PLL_RESET_A | SI5351_PLL_RESET_B); + si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, (1 << hwdata->num), 0); return 0;