From patchwork Fri Jul 28 09:53:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 9868279 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 38F5C60382 for ; Fri, 28 Jul 2017 09:55:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4104C288A8 for ; Fri, 28 Jul 2017 09:55:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 35DB2288B9; Fri, 28 Jul 2017 09:55:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DD968288A8 for ; Fri, 28 Jul 2017 09:55:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751744AbdG1Jyh (ORCPT ); Fri, 28 Jul 2017 05:54:37 -0400 Received: from mail-wm0-f48.google.com ([74.125.82.48]:38548 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751678AbdG1JxT (ORCPT ); Fri, 28 Jul 2017 05:53:19 -0400 Received: by mail-wm0-f48.google.com with SMTP id m85so113130083wma.1 for ; Fri, 28 Jul 2017 02:53:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b7i59rdVTaPJSNZY5wM3lp3p8yLkZ72JM07SsPsCAKk=; b=Wlyyqhu2NbsXX7AylgVGsuzaoTwDONGrF8kh2TO2Ds2t4HE7ArPz/2H2vUXvZwsTRe /SawBS7g23VUkCfFAqhm59s3mfIVP8Jh+Eomvsd+iGe7l1DsIq4OXA+r/wCTNQuGYD/g ONnT+3UpnGAfMpujaz6xvL1LUortwJ6oMmN9AAZDDN5ZKzPHOpr9r6E5s35eRUeRU8Bh FWYmTlqjNeBn1oICMLmgUIiPDXuewWjcj+mUerk9KoCt4qIk5jK4+kZJVunKGePmuBlL nAZ4V3GUjz0+ANhZ3FMjKibxYMgou9iQbwatt9q0jaAq/cevIlVVQ0DjAgPeKyyArc43 jYaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b7i59rdVTaPJSNZY5wM3lp3p8yLkZ72JM07SsPsCAKk=; b=iB9rhx/u7905ogocFmvZJvNtef6eSZLEcXBr8DtFhsxli6GLA8n9c1UsWVCTgHf3HO 40TGp3tfTSPEuAp2vrrWlFYsUtA4vPPL5Go/gQrSfV7PxbuBzuRqkbQviwjCL+mWY5I7 fKaVbKvLrhgRFcR2ypH8m+QXllKKKVnRW6/Pi/orHH612bMFdPsOzpGIVrANg5KTXZv6 C/wjsWWnxfzK1xGUoZF4CcoMEDqXKy7jP65QYAYT7ZFLCwAMFzBgXgkR3latWJqKotTR 9DSV/tFpMmnSCOLHTJ6w9p9TWKm65tGZY55BTRLSwWFMnPOfsRkplbVSuojgqMZrO7dt h3iQ== X-Gm-Message-State: AIVw1101NXNdTnd0RLCX0rBsdTKQpeY0WxXK+cSrl3sCbjKcv2FJn29y Ow5/PqCmlqXEOiO8 X-Received: by 10.28.29.2 with SMTP id d2mr4881153wmd.152.1501235598216; Fri, 28 Jul 2017 02:53:18 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id o30sm9899694wrb.76.2017.07.28.02.53.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Jul 2017 02:53:17 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, narmstrong@baylibre.com Cc: linux-clk@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/4] dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings Date: Fri, 28 Jul 2017 11:53:06 +0200 Message-Id: <1501235589-318-2-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1501235589-318-1-git-send-email-narmstrong@baylibre.com> References: <1501235589-318-1-git-send-email-narmstrong@baylibre.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On the first revision of the bindings, only the gates + resets were known in the AO Clock HW, but more registers used to configures AO clock are known to be spread among the AO register space. This patch adds a parent node for the entire system control zone for the AO domain then moves the clock controller as a subnode of the system control node. Signed-off-by: Neil Armstrong --- .../bindings/clock/amlogic,gxbb-aoclkc.txt | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt index a55d31b..64884ed 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt @@ -5,9 +5,11 @@ controllers within the Always-On part of the SoC. Required Properties: -- compatible: should be "amlogic,gxbb-aoclkc" -- reg: physical base address of the clock controller and length of memory - mapped region. +- compatible: value should be different for each SoC family as : + - GXBB (S905) : "amlogic,meson-gxbb-aoclkc" + - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" + - GXM (S912) : "amlogic,meson-gxm-aoclkc" + followed by the common "amlogic,meson-gx-aoclkc" - #clock-cells: should be 1. @@ -23,14 +25,22 @@ to specify the reset which they consume. All available resets are defined as preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be used in device tree sources. +Parent node should have the following properties : +- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd" +- reg: base address and size of the AO system control register space. + Example: AO Clock controller node: - clkc_AO: clock-controller@040 { - compatible = "amlogic,gxbb-aoclkc"; - reg = <0x0 0x040 0x0 0x4>; +ao_sysctrl: sys-ctrl@0 { + compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; + reg = <0x0 0x0 0x0 0x100>; + + clkc_AO: clock-controller { + compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; #clock-cells = <1>; #reset-cells = <1>; }; +}; Example: UART controller node that consumes the clock and reset generated by the clock controller: