From patchwork Tue Aug 8 18:24:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Abhishek Sahu X-Patchwork-Id: 9888933 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A084A601EB for ; Tue, 8 Aug 2017 18:28:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 92578289AB for ; Tue, 8 Aug 2017 18:28:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 87513289E0; Tue, 8 Aug 2017 18:28:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 209B0289AB for ; Tue, 8 Aug 2017 18:28:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752517AbdHHSYv (ORCPT ); Tue, 8 Aug 2017 14:24:51 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37170 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752153AbdHHSYs (ORCPT ); Tue, 8 Aug 2017 14:24:48 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id ED38660227; Tue, 8 Aug 2017 18:24:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1502216687; bh=DcTtNOIJn20ahyYQA7CkHDJm+DzQ4OskR/81JMux/X8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OfmyrZIGacLWHvTvVIh+GOJWPW/EqmF0w5CEpLnxHcXIg3mbBhloMIdEcUkF8eK5r pPJmhDcAePluGHsHeMv74QceUe2MKOp32Can1BJDogwcnK2g6NsKXR42e5RLe9v9/O B7kVY3i5Gvtc6eDHGTtEtYQPNIw6/0BiNrqj4/Dw= Received: from absahu-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: absahu@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5D694606B7; Tue, 8 Aug 2017 18:24:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1502216685; bh=DcTtNOIJn20ahyYQA7CkHDJm+DzQ4OskR/81JMux/X8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KHerUJjR2lbaCS+j+UX5DzS01aDfHrpb322UOldXGTMj4Zgy4op8ju8j0stjpe1pP Qp9jUr206Dx2BZWnW2K7IwCbTLGqx3bqt4Ll6er6lx9cWQn2Upv5mtiCV8uKHV0u4P f5ACrn5DkfNYtC2uEwDCdzV2rHvX9UVun1/q/UCc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5D694606B7 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=absahu@codeaurora.org From: Abhishek Sahu To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: andy.gross@linaro.org, david.brown@linaro.org, rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Abhishek Sahu , Taniya Das Subject: [RFC v2 05/12] clk: qcom: support for dynamic updating the PLL Date: Tue, 8 Aug 2017 23:54:10 +0530 Message-Id: <1502216657-3342-6-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1502216657-3342-1-git-send-email-absahu@codeaurora.org> References: <1502216657-3342-1-git-send-email-absahu@codeaurora.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some of the Alpha PLL’s support dynamic update in which the frequency can be changed dynamically without turning off the PLL. This dynamic update requires the following sequence 1. Write the desired values to pll_l_val and pll_alpha_val 2. Toggle pll_latch_input from low to high 3. Wait for pll_ack_latch to transition from low to high The new L and alpha values have been latched. It make take some time for the PLL to fully settle with these new values 4. Pull pll_latch_input low Signed-off-by: Rajendra Nayak Signed-off-by: Taniya Das Signed-off-by: Abhishek Sahu --- drivers/clk/qcom/clk-alpha-pll.c | 67 +++++++++++++++++++++++++++++++++++++++- drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 6694fd5..1f37bf8a 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -31,7 +31,10 @@ # define PLL_VOTE_FSM_ENA BIT(20) # define PLL_FSM_ENA BIT(20) # define PLL_VOTE_FSM_RESET BIT(21) +# define PLL_UPDATE BIT(22) +# define PLL_UPDATE_BYPASS BIT(23) # define PLL_OFFLINE_ACK BIT(28) +# define ALPHA_PLL_ACK_LATCH BIT(29) # define PLL_ACTIVE_FLAG BIT(30) # define PLL_LOCK_DET BIT(31) @@ -123,6 +126,15 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, #define wait_for_pll_offline(pll) \ wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") +#define wait_for_pll_update(pll) \ + wait_for_pll(pll, PLL_UPDATE, 1, "update") + +#define wait_for_pll_update_ack_set(pll) \ + wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") + +#define wait_for_pll_update_ack_clear(pll) \ + wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { @@ -396,6 +408,56 @@ static void clk_alpha_pll_disable(struct clk_hw *hw) return alpha_pll_calc_rate(prate, l, a, alpha_width); } +static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) +{ + u32 mode; + int ret; + + regmap_read(pll->clkr.regmap, pll_mode(pll), &mode); + + /* Latch the input to the PLL */ + regmap_update_bits(pll->clkr.regmap, pll_mode(pll), PLL_UPDATE, + PLL_UPDATE); + + /* Make sure PLL_UPDATE request goes through*/ + mb(); + + /* Wait for 2 reference cycle before checking ACK bit */ + udelay(1); + + /* + * PLL will latch the new L, Alpha and freq control word. + * PLL will respond by raising PLL_ACK_LATCH output when new programming + * has been latched in and PLL is being updated. When + * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared + * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. + */ + if (mode & PLL_UPDATE_BYPASS) { + ret = wait_for_pll_update_ack_set(pll); + if (ret) + return ret; + + regmap_update_bits(pll->clkr.regmap, pll_mode(pll), + PLL_UPDATE, 0); + + /* Make sure PLL_UPDATE request goes through*/ + mb(); + } else { + ret = wait_for_pll_update(pll); + if (ret) + return ret; + } + + ret = wait_for_pll_update_ack_clear(pll); + if (ret) + return ret; + + /* Wait for PLL output to stabilize */ + udelay(10); + + return 0; +} + static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { @@ -428,7 +490,10 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, regmap_update_bits(pll->clkr.regmap, pll_user_ctl(pll), PLL_ALPHA_EN, PLL_ALPHA_EN); - return 0; + if (!clk_hw_is_enabled(hw) || !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) + return 0; + + return clk_alpha_pll_update_latch(pll); } static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 4901d92..8b27c05 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -54,6 +54,7 @@ struct clk_alpha_pll { #define SUPPORTS_16BIT_ALPHA BIT(1) #define SUPPORTS_FSM_MODE BIT(2) #define SUPPORTS_64BIT_CONFIG_CTL BIT(3) +#define SUPPORTS_DYNAMIC_UPDATE BIT(4) u8 flags; struct clk_regmap clkr;