From patchwork Sat Sep 16 11:44:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergej Sawazki X-Patchwork-Id: 9954207 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 43039601C0 for ; Sat, 16 Sep 2017 11:46:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 30758291A5 for ; Sat, 16 Sep 2017 11:46:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 255C7291BA; Sat, 16 Sep 2017 11:46:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F2178291A5 for ; Sat, 16 Sep 2017 11:46:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751209AbdIPLqK (ORCPT ); Sat, 16 Sep 2017 07:46:10 -0400 Received: from s62.goserver.host ([37.17.224.62]:44118 "EHLO s62.goserver.host" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751185AbdIPLqK (ORCPT ); Sat, 16 Sep 2017 07:46:10 -0400 Received: from duke.fritz.box (p5B23A905.dip0.t-ipconnect.de [91.35.169.5]) by s62.goserver.host (Postfix) with ESMTPSA id A44F4BD00C55; Sat, 16 Sep 2017 13:46:08 +0200 (CEST) From: Sergej Sawazki To: sboyd@codeaurora.org, mturquette@baylibre.com, sebastian.hesselbarth@gmail.com Cc: linux@armlinux.org.uk, linux-clk@vger.kernel.org, ce3a@gmx.de, Sergej Sawazki , Rabeeh Khoury Subject: [PATCH v2 1/2] clk: si5351: Add DT property to enable PLL reset Date: Sat, 16 Sep 2017 13:44:41 +0200 Message-Id: <1505562282-9111-2-git-send-email-sergej@taudac.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505562282-9111-1-git-send-email-sergej@taudac.com> References: <1505562282-9111-1-git-send-email-sergej@taudac.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add optional output clock DT property to enable PLL reset when a clock output is enabled. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Cc: Russell King Signed-off-by: Sergej Sawazki --- Documentation/devicetree/bindings/clock/silabs,si5351.txt | 1 + drivers/clk/clk-si5351.c | 3 +++ include/linux/platform_data/si5351.h | 2 ++ 3 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt index 28b2830..157ee02 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.txt @@ -45,6 +45,7 @@ Optional child node properties: - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth divider. - silabs,pll-master: boolean, multisynth can change pll frequency. +- silabs,pll-reset: boolean, clock output can reset its pll. - silabs,disable-state : clock output disable state, shall be 0 = clock output is driven LOW when disabled 1 = clock output is driven HIGH when disabled diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 20d9076..aba2895 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -1297,6 +1297,9 @@ static int si5351_dt_parse(struct i2c_client *client, pdata->clkout[num].pll_master = of_property_read_bool(child, "silabs,pll-master"); + + pdata->clkout[num].pll_reset = + of_property_read_bool(child, "silabs,pll-reset"); } client->dev.platform_data = pdata; diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h index 533d980..da346f22 100644 --- a/include/linux/platform_data/si5351.h +++ b/include/linux/platform_data/si5351.h @@ -85,6 +85,7 @@ enum si5351_disable_state { * @multisynth_src: multisynth source clock * @clkout_src: clkout source clock * @pll_master: if true, clkout can also change pll rate + * @pll_reset: if true, clkout can reset its pll * @drive: output drive strength * @rate: initial clkout rate, or default if 0 */ @@ -94,6 +95,7 @@ struct si5351_clkout_config { enum si5351_drive_strength drive; enum si5351_disable_state disable_state; bool pll_master; + bool pll_reset; unsigned long rate; };