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Tue, 19 Sep 2017 10:03:45 +0000 (GMT) X-AuditID: cbfec7f4-f79ab6d000003290-26-59c0eb822bd9 Received: from eusync2.samsung.com ( [203.254.199.212]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 91.12.18832.18BE0C95; Tue, 19 Sep 2017 11:03:45 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OWI00F5KUM5TPC0@eusync2.samsung.com>; Tue, 19 Sep 2017 11:03:45 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Michael Turquette , Stephen Boyd , stable@vger.kernel.org Subject: [PATCH v2 RESEND] clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle Date: Tue, 19 Sep 2017 12:01:08 +0200 Message-id: <1505815279-19097-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrLIsWRmVeSWpSXmKPExsWy7djPc7pNrw9EGkx7LWSxccZ6VovrX56z Wpw/v4Hd4mPPPVaLGef3MVmsPXKX3eLiKVeLw2/aWS1+nOlmsViw8RGjA5fH+xut7B6X+3qZ PDat6mTz6NuyitHj8ya5ANYoLpuU1JzMstQifbsErozfPeuYCq7yV8y4eJelgXE+bxcjB4eE gInE6nb1LkZOIFNM4sK99WxdjFwcQgJLGSXOXFvECuF8ZpTYev0nK0SViUTf0TmMILaQwDJG iaMzXSCKGpgkDnZdZwFJsAkYSnS97WIDsUUEHCQ+f3rNCFLELHCRSWLdyaOsIKuFBTIkGhfz g9SwCKhKvJq5D2wor4CHxMyV91gglslJnDw2GewKCYEJbBKf9jcyQSRcJLrWb4a6SFji1fEt 7BC2jERnx0Gomn5GiaZWbQh7BqPEube8ELa1xOHjF8F6mQX4JCZtm84MCQpeiY42IYgSD4kZ u+YyQ9iOElcPzGCDeDhW4tn1G2wTGKUWMDKsYhRJLS3OTU8tNtErTswtLs1L10vOz93ECIzU 0/+Of9nBuPiY1SFGAQ5GJR5eibv7I4VYE8uKK3MPMUpwMCuJ8B5adCBSiDclsbIqtSg/vqg0 J7X4EKM0B4uSOK9tVFukkEB6YklqdmpqQWoRTJaJg1OqgbEySu2A4ETNR7H3T65/JF9icvHk vtVbb1lNm11u/aWqZWLslpq2x8vnOEo92Nnzg3NxvZDzoxDdNQnrgy4/Kj69lGuqKW+WNy/L 7ugND+USL09c5iERtrl6LXdY0tpnbop8fp8qd25y+Jv7X59J7cqkGwoN3XMCuJ8lCyRasfbO fvTnZP4L9QtKLMUZiYZazEXFiQAYiVGf0AIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupkluLIzCtJLcpLzFFi42I5/e/4Fd3G1wciDU4dNbLYOGM9q8X1L89Z Lc6f38Bu8bHnHqvFjPP7mCzWHrnLbnHxlKvF4TftrBY/znSzWCzY+IjRgcvj/Y1Wdo/Lfb1M HptWdbJ59G1ZxejxeZNcAGsUl01Kak5mWWqRvl0CV8bvnnVMBVf5K2ZcvMvSwDift4uRk0NC wESi7+gcRghbTOLCvfVsXYxcHEICSxglHv3fxQ7hNDFJPN35jBWkik3AUKLrbRcbiC0i4CDx +dNrRpAiZoHLTBLb1m8Ccjg4hAUyJNbddgGpYRFQlXg1cx/YBl4BD4mZK++xQGyTkzh5bDLr BEbuBYwMqxhFUkuLc9Nziw31ihNzi0vz0vWS83M3MQIDaNuxn5t3MF7aGHyIUYCDUYmHV+Da /kgh1sSy4srcQ4wSHMxKIryHFh2IFOJNSaysSi3Kjy8qzUktPsQozcGiJM7bu2d1pJBAemJJ anZqakFqEUyWiYNTqoHRteYX+ycHG+051nMe8WVOyeXy9fuwSHlqxhTbN2LTv0tN2N0vdnOB yKpfcyerxC6a22v/hjuCNTU7anoMz+Q/uz5balgbxF5ca2Be8cFUTLbO/Eba1tsy4rPWOUn6 2s3mX9Bmv+7oto9fd8zTjDjTp9ZWJjdZYNvPs8myBWkhTke2b7x2wNxQiaU4I9FQi7moOBEA jqSjMhwCAAA= X-CMS-MailID: 20170919100345eucas1p1391a495dab09faecdc2acf9635e4c42d X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-CMS-RootMailID: 20170919100345eucas1p1391a495dab09faecdc2acf9635e4c42d X-RootMTR: 20170919100345eucas1p1391a495dab09faecdc2acf9635e4c42d References: Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") added enable/disable operations to PLL clocks. Prior that VPLL and EPPL clocks were always enabled because the enable bit was never touched. Those clocks have to be enabled during suspend/resume cycle, because otherwise board fails to enter sleep mode. This patch enables them unconditionally before entering system suspend state. System restore function will set them to the previous state saved in the register cache done before that unconditional enable. Fixes: 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") CC: stable@vger.kernel.org # v4.13 Signed-off-by: Marek Szyprowski Reviewed-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski Acked-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos4.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index e40b77583c47..d8d3cb67b402 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -294,6 +294,18 @@ enum exynos4_plls { #define PLL_ENABLED (1 << 31) #define PLL_LOCKED (1 << 29) +static void exynos4_clk_enable_pll(u32 reg) +{ + u32 pll_con = readl(reg_base + reg); + pll_con |= PLL_ENABLED; + writel(pll_con, reg_base + reg); + + while (!(pll_con & PLL_LOCKED)) { + cpu_relax(); + pll_con = readl(reg_base + reg); + } +} + static void exynos4_clk_wait_for_pll(u32 reg) { u32 pll_con; @@ -315,6 +327,9 @@ static int exynos4_clk_suspend(void) samsung_clk_save(reg_base, exynos4_save_pll, ARRAY_SIZE(exynos4_clk_pll_regs)); + exynos4_clk_enable_pll(EPLL_CON0); + exynos4_clk_enable_pll(VPLL_CON0); + if (exynos4_soc == EXYNOS4210) { samsung_clk_save(reg_base, exynos4_save_soc, ARRAY_SIZE(exynos4210_clk_save));