From patchwork Thu Sep 28 17:50:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Abhishek Sahu X-Patchwork-Id: 9976549 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C6CED60568 for ; Thu, 28 Sep 2017 17:53:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B86E6296D5 for ; Thu, 28 Sep 2017 17:53:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AD1C2296D8; Thu, 28 Sep 2017 17:53:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 57CFF296D7 for ; Thu, 28 Sep 2017 17:53:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752479AbdI1RxC (ORCPT ); Thu, 28 Sep 2017 13:53:02 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50862 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752227AbdI1Rve (ORCPT ); Thu, 28 Sep 2017 13:51:34 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 8E25660C7B; Thu, 28 Sep 2017 17:51:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1506621093; bh=+IX2YTTipmD7K1sK2qYmTclOQDD7NmVN/Dej26TkSEQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lPf9+0RQYVqlxjMFCpOpYcuWmod4KPjFoL88zk4nznVZA6PSJZ2FDBNmtimNht6u1 GG/idTaJOfegEbcvp9D1pQr1/7NyEgNKp2uIbQAFAugf6utTEQ0AsdubjilYwV7X2K ALS6xWUYZ+cJi7wR2Gz2nozNr4De2QtAZgQsDzm0= Received: from absahu-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: absahu@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0B27960C6C; Thu, 28 Sep 2017 17:51:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1506621092; bh=+IX2YTTipmD7K1sK2qYmTclOQDD7NmVN/Dej26TkSEQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LRHayumk9zekX45zZB74w7gq4VcN2ruOowdp6byO4JJ0/Lg0N13UicjxHDpGnwBko 6hXIuvsBWo1VRTUe+C4lGbqNjLhCwf47J7kU5Ztef4eeXz0s0AGFA9CuiTzj1++B3q dLLtMPNAqrQHAztWAExElruPGpPC/WqsmmtaSa/E= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 0B27960C6C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=absahu@codeaurora.org From: Abhishek Sahu To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Abhishek Sahu Subject: [PATCH 09/13] clk: qcom: add flag for VCO operation Date: Thu, 28 Sep 2017 23:20:46 +0530 Message-Id: <1506621050-10129-10-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> References: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some of the Alpha PLL’s does not have VCO configuration so this patch adds the flag and does not perform VCO operation if this flag is set. Signed-off-by: Abhishek Sahu --- drivers/clk/qcom/clk-alpha-pll.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 6f2d165..bb35c60 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -139,6 +139,7 @@ struct alpha_pll_props { #define HAVE_64BIT_CONFIG_CTL BIT(0) #define SUPPORTS_DYNAMIC_UPDATE BIT(1) +#define SUPPORTS_VCO BIT(2) u8 flags; struct alpha_pll_clk_ops ops; }; @@ -527,15 +528,17 @@ static int alpha_pll_default_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); const struct pll_vco *vco; - u8 type = pll->pll_type; + u8 type = pll->pll_type, flags = pll_flags(type); u32 l, off = pll->offset, alpha_width = pll_alpha_width(type); u64 a; rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); - vco = alpha_pll_find_vco(pll, rate); - if (!vco) { - pr_err("alpha pll not in a valid vco range\n"); - return -EINVAL; + if (flags & SUPPORTS_VCO) { + vco = alpha_pll_find_vco(pll, rate); + if (!vco) { + pr_err("alpha pll not in a valid vco range\n"); + return -EINVAL; + } } regmap_write(pll->clkr.regmap, off + pll_l(type), l); @@ -549,15 +552,15 @@ static int alpha_pll_default_set_rate(struct clk_hw *hw, unsigned long rate, regmap_write(pll->clkr.regmap, off + pll_alpha(type), a); - regmap_update_bits(pll->clkr.regmap, off + pll_user_ctl(type), - PLL_VCO_MASK << PLL_VCO_SHIFT, - vco->val << PLL_VCO_SHIFT); + if (flags & SUPPORTS_VCO) + regmap_update_bits(pll->clkr.regmap, off + pll_user_ctl(type), + PLL_VCO_MASK << PLL_VCO_SHIFT, + vco->val << PLL_VCO_SHIFT); regmap_update_bits(pll->clkr.regmap, off + pll_user_ctl(type), PLL_ALPHA_EN, PLL_ALPHA_EN); - if (!clk_hw_is_enabled(hw) || - !(pll_flags(type) & SUPPORTS_DYNAMIC_UPDATE)) + if (!clk_hw_is_enabled(hw) || !(flags & SUPPORTS_DYNAMIC_UPDATE)) return 0; return clk_alpha_pll_update_latch(pll); @@ -567,12 +570,13 @@ static long alpha_pll_default_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 l, alpha_width = pll_alpha_width(pll->pll_type); + u8 type = pll->pll_type; + u32 l, alpha_width = pll_alpha_width(type); u64 a; unsigned long min_freq, max_freq; rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); - if (alpha_pll_find_vco(pll, rate)) + if (!(pll_flags(type) & SUPPORTS_VCO) || alpha_pll_find_vco(pll, rate)) return rate; min_freq = pll->vco_table[0].min_freq; @@ -721,6 +725,7 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, [PLL_STATUS] = 0x24, }, .alpha_width = 40, + .flags = SUPPORTS_VCO, .ops = { .enable = alpha_pll_default_enable, .disable = alpha_pll_default_disable,