From patchwork Thu Sep 28 17:50:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Abhishek Sahu X-Patchwork-Id: 9976557 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2DFA960365 for ; Thu, 28 Sep 2017 17:54:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1E98526E3A for ; Thu, 28 Sep 2017 17:54:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1242127BA5; Thu, 28 Sep 2017 17:54:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AAB8C26E3A for ; Thu, 28 Sep 2017 17:54:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752510AbdI1Rxs (ORCPT ); Thu, 28 Sep 2017 13:53:48 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50620 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752585AbdI1RvY (ORCPT ); Thu, 28 Sep 2017 13:51:24 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 1717360C52; Thu, 28 Sep 2017 17:51:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1506621082; bh=//g9dq/q8D3Ovbvb0O21wiVaIRmuI5X+tM6rRVCpj0c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GzwZmMInW9fJrfoEk9wojveJv6CBtH0MS1IKxzK5elogh8rJMPUctSPBhz2AK13oP DvlkjOFDSbiUOkN1j4e8bs9kWDiKdPOnFhmn2FxH2QxcMYGHVJRkAkZC4tKyjGF65p QKyGr4PDFLNLPR4B+hsmV5GPoYCONu5ODOTGFePM= Received: from absahu-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: absahu@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D1E4360C52; Thu, 28 Sep 2017 17:51:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1506621080; bh=//g9dq/q8D3Ovbvb0O21wiVaIRmuI5X+tM6rRVCpj0c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gjlCHv4Gv8IoaJAJAAnQ93S0zuM93OnZfSNW7t4aWIuMSGnTHfwUb7ATHvpQp7jHW nJb1sFiFXXelmdVE3A249r2HeAGHIdxymOo09Mt1YddHdLW8CBxRDLP1U8p/VWJ1Xh gp0OuTu/FlqcjoDve86v8cukm8SaSFag9eb6nZDQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D1E4360C52 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=absahu@codeaurora.org From: Abhishek Sahu To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Abhishek Sahu Subject: [PATCH 06/13] clk: qcom: flag for 64 bit CONFIG_CTL Date: Thu, 28 Sep 2017 23:20:43 +0530 Message-Id: <1506621050-10129-7-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> References: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some of the Alpha PLL’s (like Spark, Brammo PLL) do not have CONFIG_CTL_U register. This patch adds the flag in properties for PLL’s which have CONFIG_CTL_U register and checks the same while doing PLL initial configuration. Signed-off-by: Abhishek Sahu --- drivers/clk/qcom/clk-alpha-pll.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 78eb6bf..b33d120 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -49,6 +49,9 @@ /* Returns the Alpha register width for pll type */ #define pll_alpha_width(type) (alpha_pll_props[type].alpha_width) +/* Returns the flags for pll type */ +#define pll_flags(type) (alpha_pll_props[type].flags) + /* Returns the alpha_pll_clk_ops for pll type */ #define pll_clk_ops(hw) (alpha_pll_props[to_clk_alpha_pll(hw)-> \ pll_type].ops) @@ -130,6 +133,9 @@ struct alpha_pll_clk_ops { struct alpha_pll_props { u8 reg_offsets[PLL_MAX_REGS]; u8 alpha_width; + +#define HAVE_64BIT_CONFIG_CTL BIT(0) + u8 flags; struct alpha_pll_clk_ops ops; }; @@ -180,7 +186,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, { u32 val, mask; u32 off = pll->offset; - u8 type = pll->pll_type; + u8 type = pll->pll_type, flags = pll_flags(type); regmap_write(regmap, off + pll_l(type), config->l); regmap_write(regmap, off + pll_alpha(type), config->alpha); @@ -188,6 +194,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, regmap_write(regmap, off + pll_cfg_ctl_u(type), config->config_ctl_hi_val); + if (flags & HAVE_64BIT_CONFIG_CTL) + regmap_write(regmap, off + pll_cfg_ctl_u(type), + config->config_ctl_hi_val); + val = config->main_output_mask; val |= config->aux_output_mask; val |= config->aux2_output_mask;