From patchwork Thu Sep 28 17:50:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Abhishek Sahu X-Patchwork-Id: 9976513 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 514B760365 for ; Thu, 28 Sep 2017 17:51:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 413CE296D9 for ; Thu, 28 Sep 2017 17:51:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 31CD6296F7; Thu, 28 Sep 2017 17:51:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 66124296E6 for ; Thu, 28 Sep 2017 17:51:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752214AbdI1Rve (ORCPT ); Thu, 28 Sep 2017 13:51:34 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50788 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752611AbdI1Rvc (ORCPT ); Thu, 28 Sep 2017 13:51:32 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 90E2860C72; Thu, 28 Sep 2017 17:51:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1506621090; bh=OjPcIi6KJjMPrU8AKp61wWoAbnU8jyHr+CbVMFJVoh4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ViNsr2gayj4OPjmIM8DTnrbK1U3eg5zUVOxnfhspXREz3/IweTPe6jOcaGT+gDKpe WxJfVxuZUSMJXmxa81CiW5jsdJ/2QeVtsMtssQenV5kdZsZEV4H45TxQp0WRnAP6uH H9tEuV98sKU2nY9/UtwXdV9VL0e3rFJrMbDBODm4= Received: from absahu-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: absahu@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2482560A36; Thu, 28 Sep 2017 17:51:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1506621088; bh=OjPcIi6KJjMPrU8AKp61wWoAbnU8jyHr+CbVMFJVoh4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mZ0Ml65dRl/AfuRwbi93dYBY2vV+ENWShweLw/u2/CU/lwGzvaZD2BEAaz6rUL1il QkczqboBIh2FKGYEQlC2jF87TqRXFbJVZp8dXIibAB9lvbeETjAxmMiWH7pYZrwmZ2 nvr8deLvmf99Ua94OZZtaok/jrhTPsGE5xQAbFB8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2482560A36 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=absahu@codeaurora.org From: Abhishek Sahu To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Abhishek Sahu , Taniya Das Subject: [PATCH 08/13] clk: qcom: support for dynamic updating the PLL Date: Thu, 28 Sep 2017 23:20:45 +0530 Message-Id: <1506621050-10129-9-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> References: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some of the Alpha PLL’s support dynamic update in which the frequency can be changed dynamically without turning off the PLL. This dynamic update requires the following sequence 1. Write the desired values to pll_l_val and pll_alpha_val 2. Toggle pll_latch_input from low to high 3. Wait for pll_ack_latch to transition from low to high The new L and alpha values have been latched. It make take some time for the PLL to fully settle with these new values 4. Pull pll_latch_input low Signed-off-by: Rajendra Nayak Signed-off-by: Taniya Das Signed-off-by: Abhishek Sahu --- drivers/clk/qcom/clk-alpha-pll.c | 69 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 67 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 07030d3..6f2d165 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -31,7 +31,10 @@ # define PLL_VOTE_FSM_ENA BIT(20) # define PLL_FSM_ENA BIT(20) # define PLL_VOTE_FSM_RESET BIT(21) +# define PLL_UPDATE BIT(22) +# define PLL_UPDATE_BYPASS BIT(23) # define PLL_OFFLINE_ACK BIT(28) +# define ALPHA_PLL_ACK_LATCH BIT(29) # define PLL_ACTIVE_FLAG BIT(30) # define PLL_LOCK_DET BIT(31) @@ -134,7 +137,8 @@ struct alpha_pll_props { u8 reg_offsets[PLL_MAX_REGS]; u8 alpha_width; -#define HAVE_64BIT_CONFIG_CTL BIT(0) +#define HAVE_64BIT_CONFIG_CTL BIT(0) +#define SUPPORTS_DYNAMIC_UPDATE BIT(1) u8 flags; struct alpha_pll_clk_ops ops; }; @@ -181,6 +185,15 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, #define wait_for_pll_offline(pll) \ wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") +#define wait_for_pll_update(pll) \ + wait_for_pll(pll, PLL_UPDATE, 1, "update") + +#define wait_for_pll_update_ack_set(pll) \ + wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") + +#define wait_for_pll_update_ack_clear(pll) \ + wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { @@ -461,6 +474,54 @@ static void alpha_pll_default_disable(struct clk_hw *hw) return alpha_pll_calc_rate(prate, l, a, alpha_width); } +static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) +{ + int ret; + u32 mode, off = pll->offset; + + regmap_read(pll->clkr.regmap, off, &mode); + + /* Latch the input to the PLL */ + regmap_update_bits(pll->clkr.regmap, off, PLL_UPDATE, PLL_UPDATE); + + /* Make sure PLL_UPDATE request goes through*/ + mb(); + + /* Wait for 2 reference cycle before checking ACK bit */ + udelay(1); + + /* + * PLL will latch the new L, Alpha and freq control word. + * PLL will respond by raising PLL_ACK_LATCH output when new programming + * has been latched in and PLL is being updated. When + * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared + * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. + */ + if (mode & PLL_UPDATE_BYPASS) { + ret = wait_for_pll_update_ack_set(pll); + if (ret) + return ret; + + regmap_update_bits(pll->clkr.regmap, off, PLL_UPDATE, 0); + + /* Make sure PLL_UPDATE request goes through*/ + mb(); + } else { + ret = wait_for_pll_update(pll); + if (ret) + return ret; + } + + ret = wait_for_pll_update_ack_clear(pll); + if (ret) + return ret; + + /* Wait for PLL output to stabilize */ + udelay(10); + + return 0; +} + static int alpha_pll_default_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { @@ -495,7 +556,11 @@ static int alpha_pll_default_set_rate(struct clk_hw *hw, unsigned long rate, regmap_update_bits(pll->clkr.regmap, off + pll_user_ctl(type), PLL_ALPHA_EN, PLL_ALPHA_EN); - return 0; + if (!clk_hw_is_enabled(hw) || + !(pll_flags(type) & SUPPORTS_DYNAMIC_UPDATE)) + return 0; + + return clk_alpha_pll_update_latch(pll); } static long alpha_pll_default_round_rate(struct clk_hw *hw, unsigned long rate,