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[212.204.172.199]) by smtp.gmail.com with ESMTPSA id w2sm39361075edb.4.2018.01.01.11.43.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Jan 2018 11:43:47 -0800 (PST) From: Bryan O'Donoghue To: mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Bryan O'Donoghue , Vladimir Zapolskiy , Sylvain Lemieux , Gabriel Fernandez , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 33/34] clk: lpc32xx: change round_rate() return logic Date: Mon, 1 Jan 2018 19:43:12 +0000 Message-Id: <1514835793-1104-34-git-send-email-pure.logic@nexus-software.ie> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514835793-1104-1-git-send-email-pure.logic@nexus-software.ie> References: <1514835793-1104-1-git-send-email-pure.logic@nexus-software.ie> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch updates the round_rate() logic here to return zero instead of a negative number on error. In conjunction with higher-level changes associated with acting on the return value of clk_ops->round_rate() it is then possible to have clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of the current limitation of 1 Hz to LONG_MAX Hz. Signed-off-by: Bryan O'Donoghue Cc: Michael Turquette Cc: Stephen Boyd Cc: Vladimir Zapolskiy Cc: Sylvain Lemieux Cc: Gabriel Fernandez Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/clk/nxp/clk-lpc32xx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c index 76c17f4..0e0d258 100644 --- a/drivers/clk/nxp/clk-lpc32xx.c +++ b/drivers/clk/nxp/clk-lpc32xx.c @@ -664,17 +664,17 @@ static unsigned long clk_usb_pll_round_rate(struct clk_hw *hw, * USB divider, USB PLL N and M parameters. */ if (rate != 48000000) - return -EINVAL; + return 0; /* USB divider clock */ usb_div_hw = clk_hw_get_parent_by_index(hw, 0); if (!usb_div_hw) - return -EINVAL; + return 0; /* Main oscillator clock */ osc_hw = clk_hw_get_parent_by_index(usb_div_hw, 0); if (!osc_hw) - return -EINVAL; + return 0; o = clk_hw_get_rate(osc_hw); /* must be in range 1..20 MHz */ /* Check if valid USB divider and USB PLL parameters exists */ @@ -697,7 +697,7 @@ static unsigned long clk_usb_pll_round_rate(struct clk_hw *hw, } } - return -EINVAL; + return 0; } #define LPC32XX_DEFINE_PLL_OPS(_name, _rc, _sr, _rr) \