From patchwork Thu Jan 4 07:08:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10143985 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 748D360594 for ; Thu, 4 Jan 2018 07:08:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6552B28403 for ; Thu, 4 Jan 2018 07:08:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 58C7D28445; Thu, 4 Jan 2018 07:08:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B8B1328403 for ; Thu, 4 Jan 2018 07:08:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751880AbeADHIe (ORCPT ); Thu, 4 Jan 2018 02:08:34 -0500 Received: from mail-pl0-f68.google.com ([209.85.160.68]:37871 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751842AbeADHIb (ORCPT ); Thu, 4 Jan 2018 02:08:31 -0500 Received: by mail-pl0-f68.google.com with SMTP id s3so581494plp.4 for ; Wed, 03 Jan 2018 23:08:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2Fh7Q2xfFWDTywo2KwwOcMidvRkrvHzsu7m8ZSJMGyw=; b=O9qRjQHFO3uT3JPtOTMXUd/KPJ+Hn8fORxeDQyeY9e6K8uI86tFvDN1Wl+N0a9KN7f +nStC2tweLRJmXNWMGy4Fitzq2AOh47ypcpNS8jWuCuqBJRrKH2xGKKHwxtfXshAF2iX FyU/3bZ5/eGbZko5frzIpTf2KPxZqAEh4YWLY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2Fh7Q2xfFWDTywo2KwwOcMidvRkrvHzsu7m8ZSJMGyw=; b=gwd+i7J6e91DoAZAFGcz/pWFDll56DUYXDU1cYnL9r4DWq2pnW13X3P11X8BPhA/B+ +dIoFgPd+joFWF4JBpilxu/R27InonRcw+UqHOQgEIu9Owf1Yl1TvH7zdsWqYEBPRLqJ u1bPMCyP64FtK9HKxrC4faTvAZudgohqyLvmlulGjfJKueFhggp0KI4S7RjW0m+Q51YL UrJVVoESNJCn8jbKn2AX93PC2D9ze2wTlAsHMxjnkEJBMS6bBowWF6YC0LlYAREYI/fE wW/URz+yYgX7ph4yfcYCEXeA8+DbPRsRKgeRGHw7TlIkvo9O+nxWB82JndyYq5Nqs0Zt 8LBA== X-Gm-Message-State: AKGB3mILYvX32dU7ZaH1c4KSpFixzfQRyByYxXww0S4zQAom3EoP0S1I GY1FDYAa+0HYuoRQ2vm+NCu7GQ== X-Google-Smtp-Source: ACJfBotBxlMWxy6PP8kvf0NBuT9CiVNTrkK88hrTpZAvmsK8uZ+9R8s16UnvpHbxaxRawt+YGdwFGQ== X-Received: by 10.84.247.2 with SMTP id n2mr3733534pll.268.1515049711250; Wed, 03 Jan 2018 23:08:31 -0800 (PST) Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id a87sm6413357pfg.159.2018.01.03.23.08.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 03 Jan 2018 23:08:30 -0800 (PST) From: Chunyan Zhang To: arm@kernel.org Cc: Stephen Boyd , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chunyan Zhang Subject: [RECEND PATCH V7 12/12] arm64: dts: add clocks for SC9860 Date: Thu, 4 Jan 2018 15:08:04 +0800 Message-Id: <1515049684-23481-2-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515049684-23481-1-git-send-email-zhang.chunyan@linaro.org> References: <20171207125715.16160-1-chunyan.zhang@spreadtrum.com> <1515049684-23481-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Chunyan Zhang Some clocks on SC9860 are in the same address area with syscon devices, those are what have a property of 'sprd,syscon' which would refer to syscon devices, others would have a reg property indicated their address ranges. Signed-off-by: Chunyan Zhang --- arch/arm64/boot/dts/sprd/sc9860.dtsi | 115 +++++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/sprd/whale2.dtsi | 18 +++++- 2 files changed, 131 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index 7b7d8ce..bf03da4 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -7,6 +7,7 @@ */ #include +#include #include "whale2.dtsi" / { @@ -183,6 +184,120 @@ }; soc { + pmu_gate: pmu-gate { + compatible = "sprd,sc9860-pmu-gate"; + sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ + clocks = <&ext_26m>; + #clock-cells = <1>; + }; + + pll: pll { + compatible = "sprd,sc9860-pll"; + sprd,syscon = <&ana_regs>; /* 0x40400000 */ + clocks = <&pmu_gate 0>; + #clock-cells = <1>; + }; + + ap_clk: clock-controller@20000000 { + compatible = "sprd,sc9860-ap-clk"; + reg = <0 0x20000000 0 0x400>; + clocks = <&ext_26m>, <&pll 0>, + <&pmu_gate 0>; + #clock-cells = <1>; + }; + + aon_prediv: aon-prediv { + compatible = "sprd,sc9860-aon-prediv"; + reg = <0 0x402d0000 0 0x400>; + clocks = <&ext_26m>, <&pll 0>, + <&pmu_gate 0>; + #clock-cells = <1>; + }; + + apahb_gate: apahb-gate { + compatible = "sprd,sc9860-apahb-gate"; + sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */ + clocks = <&aon_prediv 0>; + #clock-cells = <1>; + }; + + aon_gate: aon-gate { + compatible = "sprd,sc9860-aon-gate"; + sprd,syscon = <&aon_regs>; /* 0x402e0000 */ + clocks = <&aon_prediv 0>; + #clock-cells = <1>; + }; + + aonsecure_clk: clock-controller@40880000 { + compatible = "sprd,sc9860-aonsecure-clk"; + reg = <0 0x40880000 0 0x400>; + clocks = <&ext_26m>, <&pll 0>; + #clock-cells = <1>; + }; + + agcp_gate: agcp-gate { + compatible = "sprd,sc9860-agcp-gate"; + sprd,syscon = <&agcp_regs>; /* 0x415e0000 */ + clocks = <&aon_prediv 0>; + #clock-cells = <1>; + }; + + gpu_clk: clock-controller@60200000 { + compatible = "sprd,sc9860-gpu-clk"; + reg = <0 0x60200000 0 0x400>; + clocks = <&pll 0>; + #clock-cells = <1>; + }; + + vsp_clk: clock-controller@61000000 { + compatible = "sprd,sc9860-vsp-clk"; + reg = <0 0x61000000 0 0x400>; + clocks = <&ext_26m>, <&pll 0>; + #clock-cells = <1>; + }; + + vsp_gate: vsp-gate { + compatible = "sprd,sc9860-vsp-gate"; + sprd,syscon = <&vsp_regs>; /* 0x61100000 */ + clocks = <&vsp_clk 0>; + #clock-cells = <1>; + }; + + cam_clk: clock-controller@62000000 { + compatible = "sprd,sc9860-cam-clk"; + reg = <0 0x62000000 0 0x4000>; + clocks = <&ext_26m>, <&pll 0>; + #clock-cells = <1>; + }; + + cam_gate: cam-gate { + compatible = "sprd,sc9860-cam-gate"; + sprd,syscon = <&cam_regs>; /* 0x62100000 */ + clocks = <&cam_clk 0>; + #clock-cells = <1>; + }; + + disp_clk: clock-controller@63000000 { + compatible = "sprd,sc9860-disp-clk"; + reg = <0 0x63000000 0 0x400>; + clocks = <&ext_26m>, <&pll 0>; + #clock-cells = <1>; + }; + + disp_gate: disp-gate { + compatible = "sprd,sc9860-disp-gate"; + sprd,syscon = <&disp_regs>; /* 0x63100000 */ + clocks = <&disp_clk 0>; + #clock-cells = <1>; + }; + + apapb_gate: apapb-gate { + compatible = "sprd,sc9860-apapb-gate"; + sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */ + clocks = <&ap_clk 0>; + #clock-cells = <1>; + }; + funnel@10001000 { /* SoC Funnel */ compatible = "arm,coresight-funnel", "arm,primecell"; reg = <0 0x10001000 0 0x1000>; diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi index 6ea3a75..328009c 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -106,10 +106,24 @@ }; }; - ext_26m: ext-26m { + ext_32k: ext_32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ext-32k"; + }; + + ext_26m: ext_26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; - clock-output-names = "ext_26m"; + clock-output-names = "ext-26m"; + }; + + ext_rco_100m: ext_rco_100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "ext-rco-100m"; }; };