| Message ID | 1516367470-24340-11-git-send-email-aisheng.dong@nxp.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Fri, Jan 19, 2018 at 11:11 AM, Dong Aisheng <aisheng.dong@nxp.com> wrote: Please always add a commit log. > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> > --- > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/imx7ulp-evk.dts | 87 +++++++++++++++ > arch/arm/boot/dts/imx7ulp.dtsi | 202 +++++++++++++++++++++++++++++++++++ > arch/arm/configs/imx_v6_v7_defconfig | 16 ++- > arch/arm/mach-imx/Kconfig | 9 ++ > arch/arm/mach-imx/Makefile | 1 + > arch/arm/mach-imx/common.h | 1 + > arch/arm/mach-imx/cpu.c | 3 + > arch/arm/mach-imx/mach-imx7ulp.c | 37 +++++++ > arch/arm/mach-imx/mxc.h | 1 + > arch/arm/mach-imx/pm-imx7ulp.c | 32 ++++++ > 11 files changed, 381 insertions(+), 10 deletions(-) > create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts > create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi > create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c > create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index d0381e9..3257e71 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -519,6 +519,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ > imx7d-sdb-sht11.dtb \ > imx7s-colibri-eval-v3.dtb \ > imx7s-warp.dtb > +dtb-$(CONFIG_SOC_IMX7ULP) += \ > + imx7ulp-evk.dtb > dtb-$(CONFIG_SOC_LS1021A) += \ > ls1021a-qds.dtb \ > ls1021a-twr.dtb > diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts > new file mode 100644 > index 0000000..cc4e6ef > --- /dev/null > +++ b/arch/arm/boot/dts/imx7ulp-evk.dts > @@ -0,0 +1,87 @@ > +/* > + * Copyright 2017 NXP > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. Please use SPDX identifier. > + */ > + > +/dts-v1/; > + > +#include "imx7ulp.dtsi" > + > +/ { > + model = "NXP i.MX7ULP EVK"; > + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system"; Please remove the '"Generic DT based system" entry. > + > + chosen { > + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200"; > + stdout-path = &lpuart4; Better remove bootargs. > + }; > + > + memory { memory@60000000 , otherwise building with W=1 will give you warning. Please make sure that you don't get dtc warnings with W=1. > + device_type = "memory"; > + reg = <0x60000000 0x40000000>; > + }; > +}; > + > +&lpuart4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lpuart4>; > + status = "okay"; > +}; > + > +&usdhc0 { > + pinctrl-names = "default"; > + pinctrl-0 = <>; > + pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>; > +// <&pinctrl_usdhc0_cd>, <&pinctrl_usdhc0_rst>; Just remove the line instead of commenting it. > diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi > new file mode 100644 > index 0000000..05410ba > --- /dev/null > +++ b/arch/arm/boot/dts/imx7ulp.dtsi > @@ -0,0 +1,202 @@ > +/* > + * Copyright NXP No year information? > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. Please use SPDX identifier instead. > diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig > index 0d44949..3ce8ff6 100644 > --- a/arch/arm/configs/imx_v6_v7_defconfig > +++ b/arch/arm/configs/imx_v6_v7_defconfig > @@ -41,6 +41,7 @@ CONFIG_SOC_IMX6SL=y > CONFIG_SOC_IMX6SX=y > CONFIG_SOC_IMX6UL=y > CONFIG_SOC_IMX7D=y > +CONFIG_SOC_IMX7ULP=y This should be part of a separate patch. > CONFIG_SOC_VF610=y > CONFIG_PCI=y > CONFIG_PCI_MSI=y > @@ -48,9 +49,7 @@ CONFIG_PCI_IMX6=y > CONFIG_SMP=y > CONFIG_ARM_PSCI=y > CONFIG_PREEMPT_VOLUNTARY=y > -CONFIG_AEABI=y > CONFIG_HIGHMEM=y > -CONFIG_CMA=y > CONFIG_FORCE_MAX_ZONEORDER=14 > CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" > CONFIG_KEXEC=y > @@ -81,7 +80,6 @@ CONFIG_CAN_FLEXCAN=y > CONFIG_BT=y > CONFIG_BT_HCIUART=y > CONFIG_BT_HCIUART_H4=y > -CONFIG_BT_HCIUART_LL=y > CONFIG_CFG80211=y > CONFIG_CFG80211_WEXT=y > CONFIG_MAC80211=y > @@ -90,7 +88,6 @@ CONFIG_RFKILL_INPUT=y > CONFIG_DEVTMPFS=y > CONFIG_DEVTMPFS_MOUNT=y > # CONFIG_STANDALONE is not set > -CONFIG_DMA_CMA=y > CONFIG_CMA_SIZE_MBYTES=64 > CONFIG_IMX_WEIM=y > CONFIG_CONNECTOR=y > @@ -167,9 +164,9 @@ CONFIG_MOUSE_PS2_ELANTECH=y > CONFIG_INPUT_TOUCHSCREEN=y > CONFIG_TOUCHSCREEN_ADS7846=y > CONFIG_TOUCHSCREEN_EGALAX=y > +CONFIG_TOUCHSCREEN_MAX11801=y > CONFIG_TOUCHSCREEN_IMX6UL_TSC=y > CONFIG_TOUCHSCREEN_EDT_FT5X06=y > -CONFIG_TOUCHSCREEN_MAX11801=y > CONFIG_TOUCHSCREEN_MC13783=y > CONFIG_TOUCHSCREEN_TSC2004=y > CONFIG_TOUCHSCREEN_TSC2007=y > @@ -178,7 +175,6 @@ CONFIG_TOUCHSCREEN_SX8654=y > CONFIG_TOUCHSCREEN_COLIBRI_VF50=y > CONFIG_INPUT_MISC=y > CONFIG_INPUT_MMA8450=y > -CONFIG_HID_MULTITOUCH=y > CONFIG_SERIO_SERPORT=m > # CONFIG_LEGACY_PTYS is not set > CONFIG_SERIAL_IMX=y > @@ -228,13 +224,13 @@ CONFIG_REGULATOR_GPIO=y > CONFIG_REGULATOR_MC13783=y > CONFIG_REGULATOR_MC13892=y > CONFIG_REGULATOR_PFUZE100=y > +CONFIG_RC_CORE=y > +CONFIG_RC_DEVICES=y > +CONFIG_IR_GPIO_CIR=y > CONFIG_MEDIA_SUPPORT=y > CONFIG_MEDIA_CAMERA_SUPPORT=y > -CONFIG_RC_CORE=y > CONFIG_MEDIA_CONTROLLER=y > CONFIG_VIDEO_V4L2_SUBDEV_API=y > -CONFIG_RC_DEVICES=y > -CONFIG_IR_GPIO_CIR=y > CONFIG_MEDIA_USB_SUPPORT=y > CONFIG_USB_VIDEO_CLASS=m > CONFIG_V4L_PLATFORM_DRIVERS=y > @@ -245,7 +241,6 @@ CONFIG_VIDEO_CODA=m > # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set > CONFIG_VIDEO_ADV7180=m > CONFIG_VIDEO_OV5640=m > -CONFIG_SOC_CAMERA_OV2640=y > CONFIG_IMX_IPUV3_CORE=y > CONFIG_DRM=y > CONFIG_DRM_PANEL_SIMPLE=y > @@ -283,6 +278,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=y > CONFIG_SND_SOC_TLV320AIC3X=y > CONFIG_SND_SOC_WM8960=y > CONFIG_SND_SIMPLE_CARD=y > +CONFIG_HID_MULTITOUCH=y Don't do the defconfig cleanup in the same patch. > CONFIG_USB=y > CONFIG_USB_EHCI_HCD=y > CONFIG_USB_EHCI_MXC=y > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig > index 782699e..54002c3 100644 > --- a/arch/arm/mach-imx/Kconfig > +++ b/arch/arm/mach-imx/Kconfig > @@ -554,6 +554,15 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms" > > if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M > > +config SOC_IMX7ULP > + bool "i.MX7ULP support" > + select ARM_GIC > + select CLKSRC_IMX_TPM > + select HAVE_ARM_ARCH_TIMER > + select PINCTRL_IMX7ULP > + help > + This enables support for Freescale i.MX7 Ultra Low Power processor. > + > config SOC_VF610 > bool "Vybrid Family VF610 support" > select ARM_GIC if ARCH_MULTI_V7 > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile > index 8ff7105..69c2517 100644 > --- a/arch/arm/mach-imx/Makefile > +++ b/arch/arm/mach-imx/Makefile arch/arm/mach-imx changes can also go in a different patch. -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
SGkgRmFiaW8sDQoNClRoaXMgcGF0Y2ggKFBhdGNoIDEwKSBpcyB1c2VkIGZvciB0ZXN0IGFuZCB3 YXMgc2VudCBvdXQgYnkgYWNjaWRlbnRseSwgbm90IGZvcm1hbCBvbmUuDQpJIGFsc28gZXhwbGFp bmVkIGluIGFub3RoZXIgZW1haWwuIEd1ZXNzIHlvdSBtYXkgbm90IHNlZSBpdC4NCg0KUmVhbGx5 IHNvcnJ5IGZvciB0aGUgaW5jb252ZW5pZW5jZS4NCg0KUmVnYXJkcw0KRG9uZyBBaXNoZW5nDQoN Cj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogRmFiaW8gRXN0ZXZhbSBbbWFp bHRvOmZlc3RldmFtQGdtYWlsLmNvbV0NCj4gU2VudDogVGh1cnNkYXksIEphbnVhcnkgMjUsIDIw MTggOToyMiBQTQ0KPiBUbzogQS5zLiBEb25nIDxhaXNoZW5nLmRvbmdAbnhwLmNvbT4NCj4gQ2M6 IGxpbnV4LWNsayA8bGludXgtY2xrQHZnZXIua2VybmVsLm9yZz47IEphY2t5IEJhaSA8cGluZy5i YWlAbnhwLmNvbT47DQo+IEFuc29uIEh1YW5nIDxhbnNvbi5odWFuZ0BueHAuY29tPjsgTWljaGFl bCBUdXJxdWV0dGUNCj4gPG10dXJxdWV0dGVAYmF5bGlicmUuY29tPjsgU3RlcGhlbiBCb3lkIDxz Ym95ZEBjb2RlYXVyb3JhLm9yZz47IGxpbnV4LQ0KPiBrZXJuZWwgPGxpbnV4LWtlcm5lbEB2Z2Vy Lmtlcm5lbC5vcmc+OyBkbC1saW51eC1pbXggPGxpbnV4LWlteEBueHAuY29tPjsNCj4gRmFiaW8g RXN0ZXZhbSA8ZmFiaW8uZXN0ZXZhbUBueHAuY29tPjsgU2hhd24gR3VvDQo+IDxzaGF3bmd1b0Br ZXJuZWwub3JnPjsgbW9kZXJhdGVkIGxpc3Q6QVJNL0ZSRUVTQ0FMRSBJTVggLyBNWEMgQVJNDQo+ IEFSQ0hJVEVDVFVSRSA8bGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnPg0KPiBT dWJqZWN0OiBSZTogW1BBVENIIFYzIDEwLzEwXSBhZGQgaW14N3VscCBzdXBwb3J0DQo+IA0KPiBP biBGcmksIEphbiAxOSwgMjAxOCBhdCAxMToxMSBBTSwgRG9uZyBBaXNoZW5nIDxhaXNoZW5nLmRv bmdAbnhwLmNvbT4NCj4gd3JvdGU6DQo+IA0KPiBQbGVhc2UgYWx3YXlzIGFkZCBhIGNvbW1pdCBs b2cuDQo+IA0KPiA+IFNpZ25lZC1vZmYtYnk6IERvbmcgQWlzaGVuZyA8YWlzaGVuZy5kb25nQG54 cC5jb20+DQo+IA0KPiA+IC0tLQ0KPiA+ICBhcmNoL2FybS9ib290L2R0cy9NYWtlZmlsZSAgICAg ICAgICAgfCAgIDIgKw0KPiA+ICBhcmNoL2FybS9ib290L2R0cy9pbXg3dWxwLWV2ay5kdHMgICAg fCAgODcgKysrKysrKysrKysrKysrDQo+ID4gIGFyY2gvYXJtL2Jvb3QvZHRzL2lteDd1bHAuZHRz aSAgICAgICB8IDIwMg0KPiArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKw0KPiA+ ICBhcmNoL2FybS9jb25maWdzL2lteF92Nl92N19kZWZjb25maWcgfCAgMTYgKystDQo+ID4gIGFy Y2gvYXJtL21hY2gtaW14L0tjb25maWcgICAgICAgICAgICB8ICAgOSArKw0KPiA+ICBhcmNoL2Fy bS9tYWNoLWlteC9NYWtlZmlsZSAgICAgICAgICAgfCAgIDEgKw0KPiA+ICBhcmNoL2FybS9tYWNo LWlteC9jb21tb24uaCAgICAgICAgICAgfCAgIDEgKw0KPiA+ICBhcmNoL2FybS9tYWNoLWlteC9j cHUuYyAgICAgICAgICAgICAgfCAgIDMgKw0KPiA+ICBhcmNoL2FybS9tYWNoLWlteC9tYWNoLWlt eDd1bHAuYyAgICAgfCAgMzcgKysrKysrKw0KPiA+ICBhcmNoL2FybS9tYWNoLWlteC9teGMuaCAg ICAgICAgICAgICAgfCAgIDEgKw0KPiA+ICBhcmNoL2FybS9tYWNoLWlteC9wbS1pbXg3dWxwLmMg ICAgICAgfCAgMzIgKysrKysrDQo+ID4gIDExIGZpbGVzIGNoYW5nZWQsIDM4MSBpbnNlcnRpb25z KCspLCAxMCBkZWxldGlvbnMoLSkgIGNyZWF0ZSBtb2RlDQo+ID4gMTAwNjQ0IGFyY2gvYXJtL2Jv b3QvZHRzL2lteDd1bHAtZXZrLmR0cyAgY3JlYXRlIG1vZGUgMTAwNjQ0DQo+ID4gYXJjaC9hcm0v Ym9vdC9kdHMvaW14N3VscC5kdHNpICBjcmVhdGUgbW9kZSAxMDA2NDQNCj4gPiBhcmNoL2FybS9t YWNoLWlteC9tYWNoLWlteDd1bHAuYyAgY3JlYXRlIG1vZGUgMTAwNjQ0DQo+ID4gYXJjaC9hcm0v bWFjaC1pbXgvcG0taW14N3VscC5jDQo+ID4NCj4gPiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm0vYm9v dC9kdHMvTWFrZWZpbGUgYi9hcmNoL2FybS9ib290L2R0cy9NYWtlZmlsZQ0KPiA+IGluZGV4IGQw MzgxZTkuLjMyNTdlNzEgMTAwNjQ0DQo+ID4gLS0tIGEvYXJjaC9hcm0vYm9vdC9kdHMvTWFrZWZp bGUNCj4gPiArKysgYi9hcmNoL2FybS9ib290L2R0cy9NYWtlZmlsZQ0KPiA+IEBAIC01MTksNiAr NTE5LDggQEAgZHRiLSQoQ09ORklHX1NPQ19JTVg3RCkgKz0gXA0KPiA+ICAgICAgICAgaW14N2Qt c2RiLXNodDExLmR0YiBcDQo+ID4gICAgICAgICBpbXg3cy1jb2xpYnJpLWV2YWwtdjMuZHRiIFwN Cj4gPiAgICAgICAgIGlteDdzLXdhcnAuZHRiDQo+ID4gK2R0Yi0kKENPTkZJR19TT0NfSU1YN1VM UCkgKz0gXA0KPiA+ICsgICAgICAgaW14N3VscC1ldmsuZHRiDQo+ID4gIGR0Yi0kKENPTkZJR19T T0NfTFMxMDIxQSkgKz0gXA0KPiA+ICAgICAgICAgbHMxMDIxYS1xZHMuZHRiIFwNCj4gPiAgICAg ICAgIGxzMTAyMWEtdHdyLmR0Yg0KPiA+IGRpZmYgLS1naXQgYS9hcmNoL2FybS9ib290L2R0cy9p bXg3dWxwLWV2ay5kdHMNCj4gPiBiL2FyY2gvYXJtL2Jvb3QvZHRzL2lteDd1bHAtZXZrLmR0cw0K PiA+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0DQo+ID4gaW5kZXggMDAwMDAwMC4uY2M0ZTZlZg0KPiA+ IC0tLSAvZGV2L251bGwNCj4gPiArKysgYi9hcmNoL2FybS9ib290L2R0cy9pbXg3dWxwLWV2ay5k dHMNCj4gPiBAQCAtMCwwICsxLDg3IEBADQo+ID4gKy8qDQo+ID4gKyAqIENvcHlyaWdodCAyMDE3 IE5YUA0KPiA+ICsgKg0KPiA+ICsgKiBUaGlzIHByb2dyYW0gaXMgZnJlZSBzb2Z0d2FyZTsgeW91 IGNhbiByZWRpc3RyaWJ1dGUgaXQgYW5kL29yDQo+ID4gK21vZGlmeQ0KPiA+ICsgKiBpdCB1bmRl ciB0aGUgdGVybXMgb2YgdGhlIEdOVSBHZW5lcmFsIFB1YmxpYyBMaWNlbnNlIHZlcnNpb24gMiBh cw0KPiA+ICsgKiBwdWJsaXNoZWQgYnkgdGhlIEZyZWUgU29mdHdhcmUgRm91bmRhdGlvbi4NCj4g DQo+IFBsZWFzZSB1c2UgU1BEWCBpZGVudGlmaWVyLg0KPiANCj4gDQo+ID4gKyAqLw0KPiA+ICsN Cj4gPiArL2R0cy12MS87DQo+ID4gKw0KPiA+ICsjaW5jbHVkZSAiaW14N3VscC5kdHNpIg0KPiA+ ICsNCj4gPiArLyB7DQo+ID4gKyAgICAgICBtb2RlbCA9ICJOWFAgaS5NWDdVTFAgRVZLIjsNCj4g PiArICAgICAgIGNvbXBhdGlibGUgPSAiZnNsLGlteDd1bHAtZXZrIiwgImZzbCxpbXg3dWxwIiwg IkdlbmVyaWMgRFQNCj4gPiArYmFzZWQgc3lzdGVtIjsNCj4gDQo+IFBsZWFzZSByZW1vdmUgdGhl ICciR2VuZXJpYyBEVCBiYXNlZCBzeXN0ZW0iIGVudHJ5Lg0KPiANCj4gDQo+ID4gKw0KPiA+ICsg ICAgICAgY2hvc2VuIHsNCj4gPiArICAgICAgICAgICAgICAgYm9vdGFyZ3MgPSAiY29uc29sZT10 dHlMUDAsMTE1MjAwDQo+IGVhcmx5Y29uPWxwdWFydDMyLDB4NDAyRDAwMTAsMTE1MjAwIjsNCj4g PiArICAgICAgICAgICAgICAgc3Rkb3V0LXBhdGggPSAmbHB1YXJ0NDsNCj4gDQo+IEJldHRlciBy ZW1vdmUgYm9vdGFyZ3MuDQo+IA0KPiANCj4gPiArICAgICAgIH07DQo+ID4gKw0KPiA+ICsgICAg ICAgbWVtb3J5IHsNCj4gDQo+IG1lbW9yeUA2MDAwMDAwMCAsIG90aGVyd2lzZSBidWlsZGluZyB3 aXRoIFc9MSB3aWxsIGdpdmUgeW91IHdhcm5pbmcuDQo+IA0KPiBQbGVhc2UgbWFrZSBzdXJlIHRo YXQgeW91IGRvbid0IGdldCBkdGMgd2FybmluZ3Mgd2l0aCBXPTEuDQo+IA0KPiA+ICsgICAgICAg ICAgICAgICBkZXZpY2VfdHlwZSA9ICJtZW1vcnkiOw0KPiA+ICsgICAgICAgICAgICAgICByZWcg PSA8MHg2MDAwMDAwMCAweDQwMDAwMDAwPjsNCj4gPiArICAgICAgIH07DQo+ID4gK307DQo+ID4g Kw0KPiA+ICsmbHB1YXJ0NCB7DQo+ID4gKyAgICAgICBwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQi Ow0KPiA+ICsgICAgICAgcGluY3RybC0wID0gPCZwaW5jdHJsX2xwdWFydDQ+Ow0KPiA+ICsgICAg ICAgc3RhdHVzID0gIm9rYXkiOw0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArJnVzZGhjMCB7DQo+ID4g KyAgICAgICBwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOw0KPiA+ICsgICAgICAgcGluY3RybC0w ID0gPD47DQo+ID4gKyAgICAgICBwaW5jdHJsLTAgPSA8JnBpbmN0cmxfdXNkaGMwX2NtZF9kYXRh PiwgPCZwaW5jdHJsX3VzZGhjMF9jbGs+Ow0KPiA+ICsvLyAgICAgICAgICAgICAgICAgPCZwaW5j dHJsX3VzZGhjMF9jZD4sIDwmcGluY3RybF91c2RoYzBfcnN0PjsNCj4gDQo+IEp1c3QgcmVtb3Zl IHRoZSBsaW5lIGluc3RlYWQgb2YgY29tbWVudGluZyBpdC4NCj4gDQo+ID4gZGlmZiAtLWdpdCBh L2FyY2gvYXJtL2Jvb3QvZHRzL2lteDd1bHAuZHRzaQ0KPiA+IGIvYXJjaC9hcm0vYm9vdC9kdHMv aW14N3VscC5kdHNpIG5ldyBmaWxlIG1vZGUgMTAwNjQ0IGluZGV4DQo+ID4gMDAwMDAwMC4uMDU0 MTBiYQ0KPiA+IC0tLSAvZGV2L251bGwNCj4gPiArKysgYi9hcmNoL2FybS9ib290L2R0cy9pbXg3 dWxwLmR0c2kNCj4gPiBAQCAtMCwwICsxLDIwMiBAQA0KPiA+ICsvKg0KPiA+ICsgKiBDb3B5cmln aHQgTlhQDQo+IA0KPiBObyB5ZWFyIGluZm9ybWF0aW9uPw0KPiANCj4gDQo+ID4gKyAqDQo+ID4g KyAqIFRoaXMgcHJvZ3JhbSBpcyBmcmVlIHNvZnR3YXJlOyB5b3UgY2FuIHJlZGlzdHJpYnV0ZSBp dCBhbmQvb3INCj4gPiArIG1vZGlmeQ0KPiA+ICsgKiBpdCB1bmRlciB0aGUgdGVybXMgb2YgdGhl IEdOVSBHZW5lcmFsIFB1YmxpYyBMaWNlbnNlIHZlcnNpb24gMiBhcw0KPiA+ICsgKiBwdWJsaXNo ZWQgYnkgdGhlIEZyZWUgU29mdHdhcmUgRm91bmRhdGlvbi4NCj4gDQo+IA0KPiBQbGVhc2UgdXNl IFNQRFggaWRlbnRpZmllciBpbnN0ZWFkLg0KPiANCj4gPiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm0v Y29uZmlncy9pbXhfdjZfdjdfZGVmY29uZmlnDQo+ID4gYi9hcmNoL2FybS9jb25maWdzL2lteF92 Nl92N19kZWZjb25maWcNCj4gPiBpbmRleCAwZDQ0OTQ5Li4zY2U4ZmY2IDEwMDY0NA0KPiA+IC0t LSBhL2FyY2gvYXJtL2NvbmZpZ3MvaW14X3Y2X3Y3X2RlZmNvbmZpZw0KPiA+ICsrKyBiL2FyY2gv YXJtL2NvbmZpZ3MvaW14X3Y2X3Y3X2RlZmNvbmZpZw0KPiA+IEBAIC00MSw2ICs0MSw3IEBAIENP TkZJR19TT0NfSU1YNlNMPXkNCj4gPiAgQ09ORklHX1NPQ19JTVg2U1g9eQ0KPiA+ICBDT05GSUdf U09DX0lNWDZVTD15DQo+ID4gIENPTkZJR19TT0NfSU1YN0Q9eQ0KPiA+ICtDT05GSUdfU09DX0lN WDdVTFA9eQ0KPiANCj4gVGhpcyBzaG91bGQgYmUgcGFydCBvZiBhIHNlcGFyYXRlIHBhdGNoLg0K PiANCj4gDQo+ID4gIENPTkZJR19TT0NfVkY2MTA9eQ0KPiA+ICBDT05GSUdfUENJPXkNCj4gPiAg Q09ORklHX1BDSV9NU0k9eQ0KPiA+IEBAIC00OCw5ICs0OSw3IEBAIENPTkZJR19QQ0lfSU1YNj15 DQo+ID4gIENPTkZJR19TTVA9eQ0KPiA+ICBDT05GSUdfQVJNX1BTQ0k9eQ0KPiA+ICBDT05GSUdf UFJFRU1QVF9WT0xVTlRBUlk9eQ0KPiA+IC1DT05GSUdfQUVBQkk9eQ0KPiA+ICBDT05GSUdfSElH SE1FTT15DQo+ID4gLUNPTkZJR19DTUE9eQ0KPiA+ICBDT05GSUdfRk9SQ0VfTUFYX1pPTkVPUkRF Uj0xNA0KPiA+ICBDT05GSUdfQ01ETElORT0ibm9pbml0cmQgY29uc29sZT10dHlteGMwLDExNTIw MCINCj4gPiAgQ09ORklHX0tFWEVDPXkNCj4gPiBAQCAtODEsNyArODAsNiBAQCBDT05GSUdfQ0FO X0ZMRVhDQU49eSAgQ09ORklHX0JUPXkNCj4gPiBDT05GSUdfQlRfSENJVUFSVD15ICBDT05GSUdf QlRfSENJVUFSVF9IND15IC0NCj4gQ09ORklHX0JUX0hDSVVBUlRfTEw9eQ0KPiA+IENPTkZJR19D Rkc4MDIxMT15ICBDT05GSUdfQ0ZHODAyMTFfV0VYVD15ICBDT05GSUdfTUFDODAyMTE9eQ0KPiBA QCAtOTAsNw0KPiA+ICs4OCw2IEBAIENPTkZJR19SRktJTExfSU5QVVQ9eSAgQ09ORklHX0RFVlRN UEZTPXkNCj4gPiBDT05GSUdfREVWVE1QRlNfTU9VTlQ9eSAgIyBDT05GSUdfU1RBTkRBTE9ORSBp cyBub3Qgc2V0DQo+ID4gLUNPTkZJR19ETUFfQ01BPXkNCj4gPiAgQ09ORklHX0NNQV9TSVpFX01C WVRFUz02NA0KPiA+ICBDT05GSUdfSU1YX1dFSU09eQ0KPiA+ICBDT05GSUdfQ09OTkVDVE9SPXkN Cj4gPiBAQCAtMTY3LDkgKzE2NCw5IEBAIENPTkZJR19NT1VTRV9QUzJfRUxBTlRFQ0g9eQ0KPiA+ IENPTkZJR19JTlBVVF9UT1VDSFNDUkVFTj15ICBDT05GSUdfVE9VQ0hTQ1JFRU5fQURTNzg0Nj15 DQo+ID4gQ09ORklHX1RPVUNIU0NSRUVOX0VHQUxBWD15DQo+ID4gK0NPTkZJR19UT1VDSFNDUkVF Tl9NQVgxMTgwMT15DQo+ID4gIENPTkZJR19UT1VDSFNDUkVFTl9JTVg2VUxfVFNDPXkNCj4gPiAg Q09ORklHX1RPVUNIU0NSRUVOX0VEVF9GVDVYMDY9eQ0KPiA+IC1DT05GSUdfVE9VQ0hTQ1JFRU5f TUFYMTE4MDE9eQ0KPiA+ICBDT05GSUdfVE9VQ0hTQ1JFRU5fTUMxMzc4Mz15DQo+ID4gIENPTkZJ R19UT1VDSFNDUkVFTl9UU0MyMDA0PXkNCj4gPiAgQ09ORklHX1RPVUNIU0NSRUVOX1RTQzIwMDc9 eQ0KPiA+IEBAIC0xNzgsNyArMTc1LDYgQEAgQ09ORklHX1RPVUNIU0NSRUVOX1NYODY1ND15DQo+ ID4gQ09ORklHX1RPVUNIU0NSRUVOX0NPTElCUklfVkY1MD15ICBDT05GSUdfSU5QVVRfTUlTQz15 DQo+ID4gQ09ORklHX0lOUFVUX01NQTg0NTA9eSAtQ09ORklHX0hJRF9NVUxUSVRPVUNIPXkNCj4g PiBDT05GSUdfU0VSSU9fU0VSUE9SVD1tICAjIENPTkZJR19MRUdBQ1lfUFRZUyBpcyBub3Qgc2V0 DQo+ID4gQ09ORklHX1NFUklBTF9JTVg9eSBAQCAtMjI4LDEzICsyMjQsMTMgQEANCj4gQ09ORklH X1JFR1VMQVRPUl9HUElPPXkNCj4gPiBDT05GSUdfUkVHVUxBVE9SX01DMTM3ODM9eSAgQ09ORklH X1JFR1VMQVRPUl9NQzEzODkyPXkNCj4gPiBDT05GSUdfUkVHVUxBVE9SX1BGVVpFMTAwPXkNCj4g PiArQ09ORklHX1JDX0NPUkU9eQ0KPiA+ICtDT05GSUdfUkNfREVWSUNFUz15DQo+ID4gK0NPTkZJ R19JUl9HUElPX0NJUj15DQo+ID4gIENPTkZJR19NRURJQV9TVVBQT1JUPXkNCj4gPiAgQ09ORklH X01FRElBX0NBTUVSQV9TVVBQT1JUPXkNCj4gPiAtQ09ORklHX1JDX0NPUkU9eQ0KPiA+ICBDT05G SUdfTUVESUFfQ09OVFJPTExFUj15DQo+ID4gIENPTkZJR19WSURFT19WNEwyX1NVQkRFVl9BUEk9 eQ0KPiA+IC1DT05GSUdfUkNfREVWSUNFUz15DQo+ID4gLUNPTkZJR19JUl9HUElPX0NJUj15DQo+ ID4gIENPTkZJR19NRURJQV9VU0JfU1VQUE9SVD15DQo+ID4gIENPTkZJR19VU0JfVklERU9fQ0xB U1M9bQ0KPiA+ICBDT05GSUdfVjRMX1BMQVRGT1JNX0RSSVZFUlM9eQ0KPiA+IEBAIC0yNDUsNyAr MjQxLDYgQEAgQ09ORklHX1ZJREVPX0NPREE9bSAgIw0KPiA+IENPTkZJR19NRURJQV9TVUJEUlZf QVVUT1NFTEVDVCBpcyBub3Qgc2V0DQo+IENPTkZJR19WSURFT19BRFY3MTgwPW0NCj4gPiBDT05G SUdfVklERU9fT1Y1NjQwPW0gLUNPTkZJR19TT0NfQ0FNRVJBX09WMjY0MD15DQo+ID4gQ09ORklH X0lNWF9JUFVWM19DT1JFPXkgIENPTkZJR19EUk09eQ0KPiBDT05GSUdfRFJNX1BBTkVMX1NJTVBM RT15IEBADQo+ID4gLTI4Myw2ICsyNzgsNyBAQCBDT05GSUdfU05EX1NPQ19DUzQyWFg4X0kyQz15 DQo+ID4gQ09ORklHX1NORF9TT0NfVExWMzIwQUlDM1g9eSAgQ09ORklHX1NORF9TT0NfV004OTYw PXkNCj4gPiBDT05GSUdfU05EX1NJTVBMRV9DQVJEPXkNCj4gPiArQ09ORklHX0hJRF9NVUxUSVRP VUNIPXkNCj4gDQo+IERvbid0IGRvIHRoZSBkZWZjb25maWcgY2xlYW51cCBpbiB0aGUgc2FtZSBw YXRjaC4NCj4gDQo+ID4gIENPTkZJR19VU0I9eQ0KPiA+ICBDT05GSUdfVVNCX0VIQ0lfSENEPXkN Cj4gPiAgQ09ORklHX1VTQl9FSENJX01YQz15DQo+ID4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtL21h Y2gtaW14L0tjb25maWcgYi9hcmNoL2FybS9tYWNoLWlteC9LY29uZmlnDQo+ID4gaW5kZXggNzgy Njk5ZS4uNTQwMDJjMyAxMDA2NDQNCj4gPiAtLS0gYS9hcmNoL2FybS9tYWNoLWlteC9LY29uZmln DQo+ID4gKysrIGIvYXJjaC9hcm0vbWFjaC1pbXgvS2NvbmZpZw0KPiA+IEBAIC01NTQsNiArNTU0 LDE1IEBAIGNvbW1lbnQgIkNvcnRleC1BL0NvcnRleC1NIGFzeW1tZXRyaWMNCj4gbXVsdGlwcm9j ZXNzaW5nIHBsYXRmb3JtcyINCj4gPg0KPiA+ICBpZiBBUkNIX01VTFRJX1Y3IHx8IEFSTV9TSU5H TEVfQVJNVjdNDQo+ID4NCj4gPiArY29uZmlnIFNPQ19JTVg3VUxQDQo+ID4gKyAgICAgICBib29s ICJpLk1YN1VMUCBzdXBwb3J0Ig0KPiA+ICsgICAgICAgc2VsZWN0IEFSTV9HSUMNCj4gPiArICAg ICAgIHNlbGVjdCBDTEtTUkNfSU1YX1RQTQ0KPiA+ICsgICAgICAgc2VsZWN0IEhBVkVfQVJNX0FS Q0hfVElNRVINCj4gPiArICAgICAgIHNlbGVjdCBQSU5DVFJMX0lNWDdVTFANCj4gPiArICAgICAg IGhlbHANCj4gPiArICAgICAgICAgVGhpcyBlbmFibGVzIHN1cHBvcnQgZm9yIEZyZWVzY2FsZSBp Lk1YNyBVbHRyYSBMb3cgUG93ZXIgcHJvY2Vzc29yLg0KPiA+ICsNCj4gPiAgY29uZmlnIFNPQ19W RjYxMA0KPiA+ICAgICAgICAgYm9vbCAiVnlicmlkIEZhbWlseSBWRjYxMCBzdXBwb3J0Ig0KPiA+ ICAgICAgICAgc2VsZWN0IEFSTV9HSUMgaWYgQVJDSF9NVUxUSV9WNyBkaWZmIC0tZ2l0DQo+ID4g YS9hcmNoL2FybS9tYWNoLWlteC9NYWtlZmlsZSBiL2FyY2gvYXJtL21hY2gtaW14L01ha2VmaWxl IGluZGV4DQo+ID4gOGZmNzEwNS4uNjljMjUxNyAxMDA2NDQNCj4gPiAtLS0gYS9hcmNoL2FybS9t YWNoLWlteC9NYWtlZmlsZQ0KPiA+ICsrKyBiL2FyY2gvYXJtL21hY2gtaW14L01ha2VmaWxlDQo+ IA0KPiBhcmNoL2FybS9tYWNoLWlteCBjaGFuZ2VzIGNhbiBhbHNvIGdvIGluIGEgZGlmZmVyZW50 IHBhdGNoLg0K -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d0381e9..3257e71 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -519,6 +519,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb-sht11.dtb \ imx7s-colibri-eval-v3.dtb \ imx7s-warp.dtb +dtb-$(CONFIG_SOC_IMX7ULP) += \ + imx7ulp-evk.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-qds.dtb \ ls1021a-twr.dtb diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts new file mode 100644 index 0000000..cc4e6ef --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -0,0 +1,87 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx7ulp.dtsi" + +/ { + model = "NXP i.MX7ULP EVK"; + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200"; + stdout-path = &lpuart4; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; +}; + +&lpuart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +&usdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <>; + pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>; +// <&pinctrl_usdhc0_cd>, <&pinctrl_usdhc0_rst>; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_lpuart4: lpuart4grp { + pins = < + IMX7ULP_PAD_PTC3__LPUART4_RX + IMX7ULP_PAD_PTC2__LPUART4_TX + >; + bias-pull-up; + }; + + pinctrl_usdhc0_cmd_data: usdhc0_cmd_data_0_3_grp { + pins = < + IMX7ULP_PAD_PTD1__SDHC0_CMD + IMX7ULP_PAD_PTD2__SDHC0_CLK + IMX7ULP_PAD_PTD7__SDHC0_D3 + IMX7ULP_PAD_PTD8__SDHC0_D2 + IMX7ULP_PAD_PTD9__SDHC0_D1 + IMX7ULP_PAD_PTD10__SDHC0_D0 + >; + drive-strength = <1>; + bias-pull-up; + }; + + pinctrl_usdhc0_clk: usdhc0_clk_grp { + pins = < + IMX7ULP_PAD_PTD2__SDHC0_CLK + >; + drive-strength = <1>; + bias-pull-down; + }; + + pinctrl_usdhc0_cd: usdhc0_gpios_cd_grp { + pins = < + IMX7ULP_PAD_PTC10__PTC10 /* USDHC0 CD */ + >; + nxp,input-buffer-enable; + bias-pull-up; + }; + + pinctrl_usdhc0_rst: usdhc0_gpios_rst_grp { + pins = < + IMX7ULP_PAD_PTD0__PTD0 /* USDHC0 RST */ + >; + nxp,output-buffer-enable; + bias-pull-up; + }; +}; diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi new file mode 100644 index 0000000..05410ba --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -0,0 +1,202 @@ +/* + * Copyright NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/clock/imx7ulp-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "skeleton.dtsi" + +#include "imx7ulp-pinfunc.h" + +/ { + interrupt-parent = <&intc>; + + aliases { + serial0 = &lpuart4; + serial1 = &lpuart6; + serial2 = &lpuart5; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + }; + + intc: interrupt-controller@40021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x40021000 0x1000>, + <0x40022000 0x100>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + rosc: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + clock-frequency = <32768>; + clock-output-names = "rosc"; + #clock-cells = <0>; + }; + + sosc: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + clock-frequency = <24000000>; + clock-output-names = "sosc"; + #clock-cells = <0>; + }; + + sirc: clock@2 { + compatible = "fixed-clock"; + reg = <2>; + clock-frequency = <16000000>; + clock-output-names = "sirc"; + #clock-cells = <0>; + }; + + firc: clock@3 { + compatible = "fixed-clock"; + reg = <3>; + clock-frequency = <48000000>; + clock-output-names = "firc"; + #clock-cells = <0>; + }; + + upll: clock@4 { + compatible = "fixed-clock"; + reg = <4>; + clock-frequency = <480000000>; + clock-output-names = "upll"; + #clock-cells = <0>; + }; + + mpll: clock@5 { + compatible = "fixed-clock"; + reg = <5>; + clock-frequency = <480000000>; + clock-output-names = "mpll"; + #clock-cells = <0>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&intc>; + clock-frequency = <1000000>; + status = "disabled"; + }; + + sram: sram@20000000 { + compatible = "fsl,lpm-sram"; + reg = <0x20008000 0x4000>; + }; + + ahbbridge0: ahb-bridge0@40000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x800000>; + ranges; + + lpuart4: serial@402D0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402D0000 0x1000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPUART4>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>; + assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>; + assigned-clock-rates = <24000000>; + status = "disabled"; + }; + + lpuart5: serial@402E0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402E0000 0x1000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + tpm5: tpm@40260000 { + compatible = "fsl,imx7ulp-tpm"; + reg = <0x40260000 0x1000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, + <&clks IMX7ULP_CLK_LPTPM5>; + clock-names = "ipg", "per"; + }; + + usdhc0: usdhc@40370000 { + compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x40370000 0x10000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, + <&clks IMX7ULP_CLK_NIC1_DIV>, + <&clks IMX7ULP_CLK_USDHC0>; + clock-names ="ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + clks: scg1@403e0000 { + compatible = "fsl,imx7ulp-clock"; + reg = <0x403e0000 0x10000>, + <0x403f0000 0x10000>, + <0x40b30000 0x10000>; + reg-names = "scg1", "pcc2", "pcc3"; + clocks = <&rosc>, <&sosc>, <&sirc>, + <&firc>, <&upll>, <&mpll>; + clock-names = "rosc", "sosc", "sirc", + "firc", "upll", "mpll"; + assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>, + <&clks IMX7ULP_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC_BUS_CLK>, + <&clks IMX7ULP_CLK_NIC1_DIV>; + #clock-cells = <1>; + }; + + smc1: smc1@40410000 { + compatible = "fsl,imx7ulp-smc1"; + reg = <0x40410000 0x1000>; + }; + }; + + ahbbridge1: ahb-bridge1@40800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40800000 0x800000>; + ranges; + + iomuxc1: iomuxc1@40ac0000 { + compatible = "fsl,imx7ulp-iomuxc1"; + reg = <0x40ac0000 0x1000>; + }; + + lpuart6: serial@40A60000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x40A60000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 0d44949..3ce8ff6 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -41,6 +41,7 @@ CONFIG_SOC_IMX6SL=y CONFIG_SOC_IMX6SX=y CONFIG_SOC_IMX6UL=y CONFIG_SOC_IMX7D=y +CONFIG_SOC_IMX7ULP=y CONFIG_SOC_VF610=y CONFIG_PCI=y CONFIG_PCI_MSI=y @@ -48,9 +49,7 @@ CONFIG_PCI_IMX6=y CONFIG_SMP=y CONFIG_ARM_PSCI=y CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_AEABI=y CONFIG_HIGHMEM=y -CONFIG_CMA=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" CONFIG_KEXEC=y @@ -81,7 +80,6 @@ CONFIG_CAN_FLEXCAN=y CONFIG_BT=y CONFIG_BT_HCIUART=y CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_LL=y CONFIG_CFG80211=y CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=y @@ -90,7 +88,6 @@ CONFIG_RFKILL_INPUT=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set -CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=64 CONFIG_IMX_WEIM=y CONFIG_CONNECTOR=y @@ -167,9 +164,9 @@ CONFIG_MOUSE_PS2_ELANTECH=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=y CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_MAX11801=y CONFIG_TOUCHSCREEN_IMX6UL_TSC=y CONFIG_TOUCHSCREEN_EDT_FT5X06=y -CONFIG_TOUCHSCREEN_MAX11801=y CONFIG_TOUCHSCREEN_MC13783=y CONFIG_TOUCHSCREEN_TSC2004=y CONFIG_TOUCHSCREEN_TSC2007=y @@ -178,7 +175,6 @@ CONFIG_TOUCHSCREEN_SX8654=y CONFIG_TOUCHSCREEN_COLIBRI_VF50=y CONFIG_INPUT_MISC=y CONFIG_INPUT_MMA8450=y -CONFIG_HID_MULTITOUCH=y CONFIG_SERIO_SERPORT=m # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_IMX=y @@ -228,13 +224,13 @@ CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y CONFIG_REGULATOR_PFUZE100=y +CONFIG_RC_CORE=y +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_RC_CORE=y CONFIG_MEDIA_CONTROLLER=y CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_RC_DEVICES=y -CONFIG_IR_GPIO_CIR=y CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_V4L_PLATFORM_DRIVERS=y @@ -245,7 +241,6 @@ CONFIG_VIDEO_CODA=m # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_VIDEO_ADV7180=m CONFIG_VIDEO_OV5640=m -CONFIG_SOC_CAMERA_OV2640=y CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y @@ -283,6 +278,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=y CONFIG_SND_SOC_TLV320AIC3X=y CONFIG_SND_SOC_WM8960=y CONFIG_SND_SIMPLE_CARD=y +CONFIG_HID_MULTITOUCH=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 782699e..54002c3 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -554,6 +554,15 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms" if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M +config SOC_IMX7ULP + bool "i.MX7ULP support" + select ARM_GIC + select CLKSRC_IMX_TPM + select HAVE_ARM_ARCH_TIMER + select PINCTRL_IMX7ULP + help + This enables support for Freescale i.MX7 Ultra Low Power processor. + config SOC_VF610 bool "Vybrid Family VF610 support" select ARM_GIC if ARCH_MULTI_V7 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 8ff7105..69c2517 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o +obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o ifeq ($(CONFIG_SUSPEND),y) AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index b09a2ec..b0e85df 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -128,6 +128,7 @@ void imx6dl_pm_init(void); void imx6sl_pm_init(void); void imx6sx_pm_init(void); void imx6ul_pm_init(void); +void imx7ulp_pm_init(void); #ifdef CONFIG_PM void imx51_pm_init(void); diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index d4e55f2..46f344f 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -138,6 +138,9 @@ struct device * __init imx_soc_device_init(void) case MXC_CPU_IMX7D: soc_id = "i.MX7D"; break; + case MXC_CPU_IMX7ULP: + soc_id = "i.MX7ULP"; + break; default: soc_id = "Unknown"; } diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c new file mode 100644 index 0000000..9f7a25c --- /dev/null +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/irqchip.h> +#include <linux/of_platform.h> +#include <asm/mach/arch.h> + +#include "common.h" +#include "hardware.h" + +static void __init imx7ulp_init_machine(void) +{ + imx7ulp_pm_init(); + + mxc_set_cpu_type(MXC_CPU_IMX7ULP); + imx_print_silicon_rev("i.MX7ULP", IMX_CHIP_REVISION_1_0); + of_platform_default_populate(NULL, NULL, imx_soc_device_init()); +} + +static const char *const imx7ulp_dt_compat[] __initconst = { + "fsl,imx7ulp", + NULL, +}; + +DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)") + .init_machine = imx7ulp_init_machine, + .dt_compat = imx7ulp_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index e00d626..ac9677b 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -41,6 +41,7 @@ #define MXC_CPU_IMX6UL 0x64 #define MXC_CPU_IMX6ULL 0x65 #define MXC_CPU_IMX7D 0x72 +#define MXC_CPU_IMX7ULP 0xff #define IMX_DDR_TYPE_LPDDR2 1 diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c new file mode 100644 index 0000000..00401e0 --- /dev/null +++ b/arch/arm/mach-imx/pm-imx7ulp.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> + +#define SMC_PMCTRL 0x10 +#define BP_PMCTRL_PSTOPO 16 +#define PSTOPO_PSTOP3 0x3 + +void __init imx7ulp_pm_init(void) +{ + struct device_node *np; + void __iomem *smc1_base; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1"); + smc1_base = of_iomap(np, 0); + WARN_ON(!smc1_base); + + /* Partial Stop mode 3 with system/bus clock enabled */ + writel_relaxed(PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO, smc1_base + SMC_PMCTRL); +}
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx7ulp-evk.dts | 87 +++++++++++++++ arch/arm/boot/dts/imx7ulp.dtsi | 202 +++++++++++++++++++++++++++++++++++ arch/arm/configs/imx_v6_v7_defconfig | 16 ++- arch/arm/mach-imx/Kconfig | 9 ++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/common.h | 1 + arch/arm/mach-imx/cpu.c | 3 + arch/arm/mach-imx/mach-imx7ulp.c | 37 +++++++ arch/arm/mach-imx/mxc.h | 1 + arch/arm/mach-imx/pm-imx7ulp.c | 32 ++++++ 11 files changed, 381 insertions(+), 10 deletions(-) create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c