From patchwork Wed Jan 24 12:45:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 10182441 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 768F260567 for ; Wed, 24 Jan 2018 12:45:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 71A9620856 for ; Wed, 24 Jan 2018 12:45:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 660C9237A5; Wed, 24 Jan 2018 12:45:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EB4FF228C8 for ; Wed, 24 Jan 2018 12:45:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933644AbeAXMpr (ORCPT ); Wed, 24 Jan 2018 07:45:47 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:10147 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933386AbeAXMpq (ORCPT ); Wed, 24 Jan 2018 07:45:46 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 24 Jan 2018 04:46:10 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 24 Jan 2018 04:46:35 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 24 Jan 2018 04:46:35 -0800 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 24 Jan 2018 12:45:45 +0000 Received: from tbergstrom-lnx.Nvidia.com (10.21.24.170) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 24 Jan 2018 12:45:41 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id 4DDB0F80F99; Wed, 24 Jan 2018 14:45:41 +0200 (EET) From: Peter De Schrijver To: , , , CC: Peter De Schrijver Subject: [PATCH v2 2/6] clk: tegra: DT align parameter for CVB calculation Date: Wed, 24 Jan 2018 14:45:34 +0200 Message-ID: <1516797938-32044-4-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516797938-32044-1-git-send-email-pdeschrijver@nvidia.com> References: <1516797938-32044-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When using a PWM controlled regulator, the voltage step and offset are determined by the regulator IC in use. This is specified in DT rather than fixed in the CVB table. Hence pass this information to the CVB table calculation function. For backwards compatibility the table values are used if the corresponding parameter is 0. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 23 +++++++++++++++++++++-- drivers/clk/tegra/cvb.c | 18 ++++++++++++++---- drivers/clk/tegra/cvb.h | 5 +++-- 3 files changed, 38 insertions(+), 8 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 440eb8d..6205ce1 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -111,6 +111,7 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) struct tegra_dfll_soc_data *soc; const struct of_device_id *of_id; const struct dfll_fcpu_data *fcpu_data; + struct rail_alignment align; of_id = of_match_device(tegra124_dfll_fcpu_of_match, &pdev->dev); fcpu_data = of_id->data; @@ -135,12 +136,30 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) return -ENODEV; } + err = of_property_read_u32(pdev->dev.of_node, "nvidia,align-offset-uv", + &align.offset_uv); + if (err < 0) { + dev_err(&pdev->dev, + "offset uv not found, default to table value\n"); + align.offset_uv = 0; + } + + err = of_property_read_u32(pdev->dev.of_node, "nvidia,align-step-uv", + &align.step_uv); + if (err < 0) { + dev_err(&pdev->dev, + "step uv not found, default to table value\n"); + align.step_uv = 0; + } + soc->max_freq = fcpu_data->cpu_max_freq_table[speedo_id]; soc->cvb = tegra_cvb_add_opp_table(soc->dev, fcpu_data->cpu_cvb_tables, fcpu_data->cpu_cvb_tables_size, - process_id, speedo_id, speedo_value, - soc->max_freq); + &align, process_id, speedo_id, + speedo_value, soc->max_freq); + soc->alignment = align; + if (IS_ERR(soc->cvb)) { dev_err(&pdev->dev, "couldn't add OPP table: %ld\n", PTR_ERR(soc->cvb)); diff --git a/drivers/clk/tegra/cvb.c b/drivers/clk/tegra/cvb.c index da9e8e7..561012a 100644 --- a/drivers/clk/tegra/cvb.c +++ b/drivers/clk/tegra/cvb.c @@ -62,11 +62,19 @@ static int round_voltage(int mv, const struct rail_alignment *align, int up) } static int build_opp_table(struct device *dev, const struct cvb_table *table, + struct rail_alignment *align, int speedo_value, unsigned long max_freq) { - const struct rail_alignment *align = &table->alignment; int i, ret, dfll_mv, min_mv, max_mv; + if (!align->step_uv) + align->step_uv = table->alignment.step_uv; + if (!align->step_uv) + return -EINVAL; + + if (!align->offset_uv) + align->offset_uv = table->alignment.offset_uv; + min_mv = round_voltage(table->min_millivolts, align, UP); max_mv = round_voltage(table->max_millivolts, align, DOWN); @@ -109,8 +117,9 @@ static int build_opp_table(struct device *dev, const struct cvb_table *table, */ const struct cvb_table * tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *tables, - size_t count, int process_id, int speedo_id, - int speedo_value, unsigned long max_freq) + size_t count, struct rail_alignment *align, + int process_id, int speedo_id, int speedo_value, + unsigned long max_freq) { size_t i; int ret; @@ -124,7 +133,8 @@ static int build_opp_table(struct device *dev, const struct cvb_table *table, if (table->process_id != -1 && table->process_id != process_id) continue; - ret = build_opp_table(dev, table, speedo_value, max_freq); + ret = build_opp_table(dev, table, align, speedo_value, + max_freq); return ret ? ERR_PTR(ret) : table; } diff --git a/drivers/clk/tegra/cvb.h b/drivers/clk/tegra/cvb.h index c1f0779..cfa110f 100644 --- a/drivers/clk/tegra/cvb.h +++ b/drivers/clk/tegra/cvb.h @@ -59,8 +59,9 @@ struct cvb_table { const struct cvb_table * tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *cvb_tables, - size_t count, int process_id, int speedo_id, - int speedo_value, unsigned long max_freq); + size_t count, struct rail_alignment *align, + int process_id, int speedo_id, int speedo_value, + unsigned long max_freq); void tegra_cvb_remove_opp_table(struct device *dev, const struct cvb_table *table, unsigned long max_freq);