From patchwork Fri Feb 2 14:03:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel FERNANDEZ X-Patchwork-Id: 10196719 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4AEB76037D for ; Fri, 2 Feb 2018 14:04:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3AB9228BFE for ; Fri, 2 Feb 2018 14:04:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2F8E728E66; Fri, 2 Feb 2018 14:04:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CE2E428BFE for ; Fri, 2 Feb 2018 14:04:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752180AbeBBOEr (ORCPT ); Fri, 2 Feb 2018 09:04:47 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:51480 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751915AbeBBOEl (ORCPT ); Fri, 2 Feb 2018 09:04:41 -0500 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w12E3pgK028128; Fri, 2 Feb 2018 15:04:20 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2fvr42rg2f-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 02 Feb 2018 15:04:20 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A9AD034; Fri, 2 Feb 2018 14:04:19 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag4node2.st.com [10.75.127.11]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 88EF75228; Fri, 2 Feb 2018 14:04:19 +0000 (GMT) Received: from localhost (10.75.127.47) by SFHDAG4NODE2.st.com (10.75.127.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 2 Feb 2018 15:04:18 +0100 From: To: Rob Herring , Mark Rutland , Lee Jones , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Gabriel Fernandez CC: , , , , , Subject: [PATCH 13/14] clk: stm32mp1: add MCO clocks Date: Fri, 2 Feb 2018 15:03:41 +0100 Message-ID: <1517580222-23301-14-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517580222-23301-1-git-send-email-gabriel.fernandez@st.com> References: <1517580222-23301-1-git-send-email-gabriel.fernandez@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG4NODE2.st.com (10.75.127.11) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-02_04:, , signatures=0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gabriel Fernandez Two micro-controller clock output (MCO) pins are available: MCO1 and MCO2. For each output, it is possible to select a clock source. The selected clock can be divided thanks to configurable prescaler. Signed-off-by: Gabriel Fernandez --- drivers/clk/clk-stm32mp1.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 1cb06b0..0402a0e 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -1188,6 +1188,16 @@ static struct clk_hw *_clk_register_cktim(struct device *dev, _MUX(_mux_offset, _mux_bit, _mux_width, 0),\ } +#define _GATEMUXDIV(_gate_offset, _bit_idx,\ + _mux_offset, _mux_bit, _mux_width,\ + _div_offset, _div_bit, _div_width\ + )\ +{\ + _DIV(_div_offset, _div_bit, _div_width, 0),\ + _GATE(_gate_offset, _bit_idx, 0),\ + _MUX(_mux_offset, _mux_bit, _mux_width, 0),\ +} + #define _MP1_GATE(_gate_offset, _bit_idx, _flags)\ _GATE_OPS(_gate_offset, _bit_idx, _flags, &mp1_gate_clk_ops) @@ -1543,6 +1553,19 @@ static struct clk_hw *_clk_register_cktim(struct device *dev, COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT, _GATEMUX(RCC_BDCR, 20, RCC_BDCR, 16, 2)), + + /* MCO clocks */ + COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE | + CLK_SET_RATE_NO_REPARENT, + _GATEMUXDIV(RCC_MCO1CFGR, 12, + RCC_MCO1CFGR, 0, 3, + RCC_MCO1CFGR, 4, 4)), + + COMPOSITE(CK_MCO2, "ck_mco2", mco2_src, CLK_OPS_PARENT_ENABLE | + CLK_SET_RATE_NO_REPARENT, + _GATEMUXDIV(RCC_MCO2CFGR, 12, + RCC_MCO2CFGR, 0, 3, + RCC_MCO2CFGR, 4, 4)), }; struct stm32_clock_match_data {