From patchwork Fri Feb 2 14:03:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel FERNANDEZ X-Patchwork-Id: 10196725 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EDFF76037D for ; Fri, 2 Feb 2018 14:04:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DD50928E66 for ; Fri, 2 Feb 2018 14:04:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D1E5028E68; Fri, 2 Feb 2018 14:04:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3E8AD28E66 for ; Fri, 2 Feb 2018 14:04:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751878AbeBBOEx (ORCPT ); Fri, 2 Feb 2018 09:04:53 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:1859 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752136AbeBBOEl (ORCPT ); Fri, 2 Feb 2018 09:04:41 -0500 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w12Dwhr6011346; Fri, 2 Feb 2018 15:04:10 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2fvb1x4r8v-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 02 Feb 2018 15:04:10 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C8DBD38; Fri, 2 Feb 2018 14:04:09 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag4node2.st.com [10.75.127.11]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 88655522A; Fri, 2 Feb 2018 14:04:09 +0000 (GMT) Received: from localhost (10.75.127.45) by SFHDAG4NODE2.st.com (10.75.127.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 2 Feb 2018 15:04:08 +0100 From: To: Rob Herring , Mark Rutland , Lee Jones , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Gabriel Fernandez CC: , , , , , Subject: [PATCH 01/14] dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings Date: Fri, 2 Feb 2018 15:03:29 +0100 Message-ID: <1517580222-23301-2-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517580222-23301-1-git-send-email-gabriel.fernandez@st.com> References: <1517580222-23301-1-git-send-email-gabriel.fernandez@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG1NODE1.st.com (10.75.127.1) To SFHDAG4NODE2.st.com (10.75.127.11) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-02_04:, , signatures=0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gabriel Fernandez The RCC block is responsible of the management of the clock and reset generation for the complete circuit. Signed-off-by: Gabriel Fernandez --- .../devicetree/bindings/mfd/st,stm32-rcc.txt | 85 ++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt new file mode 100644 index 0000000..28017a1 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt @@ -0,0 +1,85 @@ +STMicroelectronics STM32 Peripheral Reset Clock Controller +========================================================== + +The RCC IP is both a reset and a clock controller. + +Please also refer to reset.txt for common reset controller binding usage. + +Please also refer to clock-bindings.txt for common clock controller +binding usage. + + +Required properties: +- compatible: "simple-mfd", "syscon" +- reg: should be register base and length as documented in the datasheet + +- Sub-nodes: + - compatible: "st,stm32mp1-rcc-clk" + - #clock-cells: 1, device nodes should specify the clock in their + "clocks" property, containing a phandle to the clock device node, + an index specifying the clock to use. + + - compatible: "st,stm32mp1-rcc-rst" + - #reset-cells: Shall be 1 + +Example: + rcc: rcc@50000000 { + compatible = "syscon", "simple-mfd"; + reg = <0x50000000 0x1000>; + + rcc_clk: rcc-clk@50000000 { + #clock-cells = <1>; + compatible = "st,stm32mp1-rcc-clk"; + }; + + rcc_rst: rcc-reset@50000000 { + #reset-cells = <1>; + compatible = "st,stm32mp1-rcc-rst"; + }; + }; + +Specifying clocks +================= + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/stm32mp1-clks.h header and can be used in device +tree sources. + +Example: + + /* Accessing DMA1 clock */ + ... { + clocks = <&rcc_clk DMA1> + }; + + /* Accessing SPI6 kernel clock */ + ... { + clocks = <&rcc_clk SPI6_K> + }; + +Specifying softreset control of devices +======================================= + +Device nodes should specify the reset channel required in their "resets" +property, containing a phandle to the reset device node and an index specifying +which channel to use. +The index is the bit number within the RCC registers bank, starting from RCC +base address. +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register. + +For example on STM32MP1, for LTDC reset: + ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset + = 0x180 / 4 * 32 + 0 = 3072 + +The list of valid indices for STM32MP1 is available in: +include/dt-bindings/reset-controller/stm32mp1-resets.h + +This file implements defines like: +#define LTDC_R 3072 + +example: + + ltdc { + resets = <&rcc_rst LTDC_R>; + };