From patchwork Tue Feb 13 13:28:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 10216525 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8B3E860329 for ; Tue, 13 Feb 2018 14:57:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7C5C62843C for ; Tue, 13 Feb 2018 14:57:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6D625287B3; Tue, 13 Feb 2018 14:57:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9F7392843C for ; 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vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=fail action=none header.from=nxp.com; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1BFFO11FD029.mail.protection.outlook.com (10.58.144.92) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.485.12 via Frontend Transport; Tue, 13 Feb 2018 14:55:42 +0000 Received: from b29396-OptiPlex-7040.ap.freescale.net (b29396-OptiPlex-7040.ap.freescale.net [10.192.242.1]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id w1DDSdTP007059; Tue, 13 Feb 2018 06:28:52 -0700 From: Dong Aisheng To: CC: , , , , , , , Dong Aisheng Subject: [PATCH RESEND V3 4/9] clk: imx: add pfdv2 support Date: Tue, 13 Feb 2018 21:28:09 +0800 Message-ID: <1518528494-25723-5-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518528494-25723-1-git-send-email-aisheng.dong@nxp.com> References: <1518528494-25723-1-git-send-email-aisheng.dong@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131630073428278599; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB470 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pfdv2 can only be operated when clk is gated. Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by: Dong Aisheng --- ChangeLog: v2->v3: * no changes v1->v2: * change to readl_poll_timeout * add pfd lock to protect share reg access between rate and enable/disable operations and multiple pfd instances. * use clk_hw_register --- drivers/clk/imx/Makefile | 3 +- drivers/clk/imx/clk-pfdv2.c | 207 ++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 3 + 3 files changed, 212 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-pfdv2.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 2f00b03..9c04ae4 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -12,7 +12,8 @@ obj-y += \ clk-pllv2.o \ clk-pllv3.o \ clk-pllv4.o \ - clk-pfd.o + clk-pfd.o \ + clk-pfdv2.o obj-$(CONFIG_SOC_IMX1) += clk-imx1.o obj-$(CONFIG_SOC_IMX21) += clk-imx21.o diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c new file mode 100644 index 0000000..5421bdf --- /dev/null +++ b/drivers/clk/imx/clk-pfdv2.c @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * Author: Dong Aisheng + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include + +/** + * struct clk_pfdv2 - IMX PFD clock + * @clk_hw: clock source + * @reg: PFD register address + * @gate_bit: Gate bit offset + * @vld_bit: Valid bit offset + * @frac_off: PLL Fractional Divider offset + */ + +struct clk_pfdv2 { + struct clk_hw hw; + void __iomem *reg; + u8 gate_bit; + u8 vld_bit; + u8 frac_off; +}; + +#define to_clk_pfdv2(_hw) container_of(_hw, struct clk_pfdv2, hw) + +#define CLK_PFDV2_FRAC_MASK 0x3f + +#define LOCK_TIMEOUT_US USEC_PER_MSEC + +static DEFINE_SPINLOCK(pfd_lock); + +static int clk_pfdv2_wait(struct clk_pfdv2 *pfd) +{ + u32 val; + + return readl_poll_timeout(pfd->reg, val, val & pfd->vld_bit, + 0, LOCK_TIMEOUT_US); +} + +static int clk_pfdv2_enable(struct clk_hw *hw) +{ + struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); + unsigned long flags; + u32 val; + + spin_lock_irqsave(&pfd_lock, flags); + val = readl_relaxed(pfd->reg); + val &= ~pfd->gate_bit; + writel_relaxed(val, pfd->reg); + spin_unlock_irqrestore(&pfd_lock, flags); + + return clk_pfdv2_wait(pfd); +} + +static void clk_pfdv2_disable(struct clk_hw *hw) +{ + struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); + unsigned long flags; + u32 val; + + spin_lock_irqsave(&pfd_lock, flags); + val = readl_relaxed(pfd->reg); + val |= pfd->gate_bit; + writel_relaxed(val, pfd->reg); + spin_unlock_irqrestore(&pfd_lock, flags); +} + +static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); + u64 tmp = parent_rate; + u8 frac; + + frac = (readl_relaxed(pfd->reg) >> pfd->frac_off) + & CLK_PFDV2_FRAC_MASK; + + if (!frac) { + pr_debug("clk_pfdv2: %s invalid pfd frac value 0\n", + clk_hw_get_name(hw)); + return 0; + } + + tmp *= 18; + do_div(tmp, frac); + + return tmp; +} + +static long clk_pfdv2_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + u64 tmp = *prate; + u8 frac; + + tmp = tmp * 18 + rate / 2; + do_div(tmp, rate); + frac = tmp; + + if (frac < 12) + frac = 12; + else if (frac > 35) + frac = 35; + + tmp = *prate; + tmp *= 18; + do_div(tmp, frac); + + return tmp; +} + +static int clk_pfdv2_is_enabled(struct clk_hw *hw) +{ + struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); + + if (readl_relaxed(pfd->reg) & pfd->gate_bit) + return 0; + + return 1; +} + +static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); + unsigned long flags; + u64 tmp = parent_rate; + u32 val; + u8 frac; + + tmp = tmp * 18 + rate / 2; + do_div(tmp, rate); + frac = tmp; + if (frac < 12) + frac = 12; + else if (frac > 35) + frac = 35; + + spin_lock_irqsave(&pfd_lock, flags); + val = readl_relaxed(pfd->reg); + val &= ~(CLK_PFDV2_FRAC_MASK << pfd->frac_off); + val |= frac << pfd->frac_off; + writel_relaxed(val, pfd->reg); + spin_unlock_irqrestore(&pfd_lock, flags); + + return 0; +} + +static const struct clk_ops clk_pfdv2_ops = { + .enable = clk_pfdv2_enable, + .disable = clk_pfdv2_disable, + .recalc_rate = clk_pfdv2_recalc_rate, + .round_rate = clk_pfdv2_round_rate, + .set_rate = clk_pfdv2_set_rate, + .is_enabled = clk_pfdv2_is_enabled, +}; + +struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name, + void __iomem *reg, u8 idx) +{ + struct clk_init_data init; + struct clk_pfdv2 *pfd; + struct clk_hw *hw; + int ret; + + WARN_ON(idx > 3); + + pfd = kzalloc(sizeof(*pfd), GFP_KERNEL); + if (!pfd) + return ERR_PTR(-ENOMEM); + + pfd->reg = reg; + pfd->gate_bit = 1 << ((idx + 1) * 8 - 1); + pfd->vld_bit = pfd->gate_bit - 1; + pfd->frac_off = idx * 8; + + init.name = name; + init.ops = &clk_pfdv2_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = CLK_SET_RATE_GATE; + + pfd->hw.init = &init; + + hw = &pfd->hw; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(pfd); + hw = ERR_PTR(ret); + } + + return hw; +} diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 52f7c9d..ccd7181 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -60,6 +60,9 @@ struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, struct clk *imx_clk_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx); +struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name, + void __iomem *reg, u8 idx); + struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift);