From patchwork Fri May 4 08:56:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianguo Sun X-Patchwork-Id: 10380237 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 959F4603B4 for ; Fri, 4 May 2018 08:57:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8842329304 for ; Fri, 4 May 2018 08:57:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7B5282934E; Fri, 4 May 2018 08:57:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D75A729304 for ; Fri, 4 May 2018 08:57:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750733AbeEDI5F (ORCPT ); Fri, 4 May 2018 04:57:05 -0400 Received: from m12-12.163.com ([220.181.12.12]:44662 "EHLO m12-12.163.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750709AbeEDI5E (ORCPT ); Fri, 4 May 2018 04:57:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id; bh=NwoEkArqvFX/n1V7IC MMwMgQSifGOBLPtsW+rM3GOEc=; b=Ys1UZFTKyef4Z8hYZIONQtSqSk849t8CEt fmwYtXXrd8qiWj531oy2NbzXlWaGblP7WEj/dX/XTPkTwjIkc8fDyE0nanKOQvoQ AMljq5xMlNEXZDlZUqwKmjf5jJKpWZLCLl/bpq7Cgrh6ktD5QG9EQDYG3kskxacV z9a8Kvgm0= Received: from localhost.localdomain (unknown [180.111.103.171]) by smtp8 (Coremail) with SMTP id DMCowADHs3FDIOxat8d0AA--.48530S3; Fri, 04 May 2018 16:56:39 +0800 (CST) From: sunjg79@163.com To: sboyd@kernel.org, mturquette@baylibre.com Cc: shawn.guo@linaro.org, xuejiancheng@hisilicon.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jianguo Sun Subject: [PATCH] clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC Date: Fri, 4 May 2018 16:56:30 +0800 Message-Id: <1525424190-15619-1-git-send-email-sunjg79@163.com> X-Mailer: git-send-email 2.7.4 X-CM-TRANSID: DMCowADHs3FDIOxat8d0AA--.48530S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7uw4DKw48Kw4fJrWfZFW5KFg_yoW8KFy7pw 4Duw4jka4DtF4fWr97ZanxtFy3XayUGFykKFy7Z3yqq3W8t340qF47W3y3XFsrZrZ3ArZ3 XFsrKw48Gw1qvrUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jfL05UUUUU= X-Originating-IP: [180.111.103.171] X-CM-SenderInfo: xvxqywixz6il2tof0z/xtbBEQc8slaDxuS5ZQABsy Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jianguo Sun There are two USB3 host controllers on Hi3798CV200 SoC. This commit adds missing clocks for them. Signed-off-by: Jianguo Sun --- drivers/clk/hisilicon/crg-hi3798cv200.c | 17 +++++++++++++++++ include/dt-bindings/clock/histb-clock.h | 8 ++++++++ 2 files changed, 25 insertions(+) diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c index 743eec1..4fe0b2a 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c @@ -186,6 +186,23 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { CLK_SET_RATE_PARENT, 0xbc, 0, 0 }, { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m", CLK_SET_RATE_PARENT, 0xbc, 2, 0 }, + /* USB3 */ + { HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL, + CLK_SET_RATE_PARENT, 0xb0, 0, 0 }, + { HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL, + CLK_SET_RATE_PARENT, 0xb0, 4, 0 }, + { HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL, + CLK_SET_RATE_PARENT, 0xb0, 3, 0 }, + { HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL, + CLK_SET_RATE_PARENT, 0xb0, 2, 0 }, + { HISTB_USB3_BUS_CLK1, "clk_u3_bus1", NULL, + CLK_SET_RATE_PARENT, 0xb0, 16, 0 }, + { HISTB_USB3_UTMI_CLK1, "clk_u3_utmi1", NULL, + CLK_SET_RATE_PARENT, 0xb0, 20, 0 }, + { HISTB_USB3_PIPE_CLK1, "clk_u3_pipe1", NULL, + CLK_SET_RATE_PARENT, 0xb0, 19, 0 }, + { HISTB_USB3_SUSPEND_CLK1, "clk_u3_suspend1", NULL, + CLK_SET_RATE_PARENT, 0xb0, 18, 0 }, }; static struct hisi_clock_data *hi3798cv200_clk_register( diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h index fab30b3..136de24 100644 --- a/include/dt-bindings/clock/histb-clock.h +++ b/include/dt-bindings/clock/histb-clock.h @@ -62,6 +62,14 @@ #define HISTB_USB2_PHY1_REF_CLK 40 #define HISTB_USB2_PHY2_REF_CLK 41 #define HISTB_COMBPHY0_CLK 42 +#define HISTB_USB3_BUS_CLK 43 +#define HISTB_USB3_UTMI_CLK 44 +#define HISTB_USB3_PIPE_CLK 45 +#define HISTB_USB3_SUSPEND_CLK 46 +#define HISTB_USB3_BUS_CLK1 47 +#define HISTB_USB3_UTMI_CLK1 48 +#define HISTB_USB3_PIPE_CLK1 49 +#define HISTB_USB3_SUSPEND_CLK1 50 /* clocks provided by mcu CRG */ #define HISTB_MCE_CLK 1