From patchwork Wed May 9 11:32:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Nischal X-Patchwork-Id: 10389137 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CFE9B60170 for ; Wed, 9 May 2018 11:33:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BFD3E28EB2 for ; Wed, 9 May 2018 11:33:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B439728EC5; Wed, 9 May 2018 11:33:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3BD7A28EC4 for ; Wed, 9 May 2018 11:33:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934180AbeEILdD (ORCPT ); Wed, 9 May 2018 07:33:03 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:54600 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934018AbeEILdB (ORCPT ); Wed, 9 May 2018 07:33:01 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E51D560FA8; Wed, 9 May 2018 11:33:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1525865580; bh=TkUodCGCUH0qW9qOsVxKWZgwtCvAV5FVIvW3sbtWL/A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MKD7+WArbTEtcA22QZMM7mhmBBH79mMNZLDVRuT/vyt7mrr21rWNldCEOblfj6WTE uWMWSRePhPwiqo+1BzEtxUevySRkTaCo6nrZB7fhqk6/rC1l8Ylfb79sH35npgBZdR ldmVnzrmjW9Jha1nxnSZaA9tOsF7tV4OZXA09ZH8= Received: from anischal-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: anischal@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2593A60F8F; Wed, 9 May 2018 11:32:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1525865580; bh=TkUodCGCUH0qW9qOsVxKWZgwtCvAV5FVIvW3sbtWL/A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MKD7+WArbTEtcA22QZMM7mhmBBH79mMNZLDVRuT/vyt7mrr21rWNldCEOblfj6WTE uWMWSRePhPwiqo+1BzEtxUevySRkTaCo6nrZB7fhqk6/rC1l8Ylfb79sH35npgBZdR ldmVnzrmjW9Jha1nxnSZaA9tOsF7tV4OZXA09ZH8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2593A60F8F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=anischal@codeaurora.org From: Amit Nischal To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Amit Nischal Subject: [PATCH v2 1/2] dt-bindings: clock: Introduce QCOM Video clock bindings Date: Wed, 9 May 2018 17:02:30 +0530 Message-Id: <1525865551-20489-2-git-send-email-anischal@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1525865551-20489-1-git-send-email-anischal@codeaurora.org> References: <1525865551-20489-1-git-send-email-anischal@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device tree bindings for video clock controller for Qualcomm Technology Inc's SoCs. Signed-off-by: Amit Nischal --- .../devicetree/bindings/clock/qcom,videocc.txt | 19 ++++++++++++ include/dt-bindings/clock/qcom,videocc-sdm845.h | 35 ++++++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,videocc.txt create mode 100644 include/dt-bindings/clock/qcom,videocc-sdm845.h -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt new file mode 100644 index 0000000..e7c035a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt @@ -0,0 +1,19 @@ +Qualcomm Video Clock & Reset Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,sdm845-videocc" +- reg : shall contain base register location and length +- #clock-cells : from common clock binding, shall contain 1. +- #power-domain-cells : from generic power domain binding, shall contain 1. + +Optional properties : +- #reset-cells : from common reset binding, shall contain 1. + +Example: + videocc: clock-controller@ab00000 { + compatible = "qcom,sdm845-videocc"; + reg = <0xab00000 0x10000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h new file mode 100644 index 0000000..1b86816 --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-sdm845.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H + +/* VIDEO_CC clock registers */ +#define VIDEO_CC_APB_CLK 0 +#define VIDEO_CC_AT_CLK 1 +#define VIDEO_CC_QDSS_TRIG_CLK 2 +#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3 +#define VIDEO_CC_VCODEC0_AXI_CLK 4 +#define VIDEO_CC_VCODEC0_CORE_CLK 5 +#define VIDEO_CC_VCODEC1_AXI_CLK 6 +#define VIDEO_CC_VCODEC1_CORE_CLK 7 +#define VIDEO_CC_VENUS_AHB_CLK 8 +#define VIDEO_CC_VENUS_CLK_SRC 9 +#define VIDEO_CC_VENUS_CTL_AXI_CLK 10 +#define VIDEO_CC_VENUS_CTL_CORE_CLK 11 +#define VIDEO_PLL0 12 + +/* VIDEO_CC Resets */ +#define VIDEO_CC_VENUS_BCR 0 +#define VIDEO_CC_VCODEC0_BCR 1 +#define VIDEO_CC_VCODEC1_BCR 2 +#define VIDEO_CC_INTERFACE_BCR 3 + +/* VIDEO_CC GDSCRs */ +#define VENUS_GDSC 0 +#define VCODEC0_GDSC 1 +#define VCODEC1_GDSC 2 + +#endif