From patchwork Thu Jul 6 10:01:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 9827933 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CA75960361 for ; Thu, 6 Jul 2017 10:02:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B7853285E4 for ; Thu, 6 Jul 2017 10:02:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ABBDF285E8; Thu, 6 Jul 2017 10:02:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, URIBL_BLACK autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8B893285FE for ; Thu, 6 Jul 2017 10:02:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752333AbdGFKCA (ORCPT ); Thu, 6 Jul 2017 06:02:00 -0400 Received: from gloria.sntech.de ([95.129.55.99]:38774 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752042AbdGFKB7 (ORCPT ); Thu, 6 Jul 2017 06:01:59 -0400 Received: from ip9234b3c2.dynamic.kabel-deutschland.de ([146.52.179.194] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.1:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1dT3bY-0007yg-Bd; Thu, 06 Jul 2017 12:01:48 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Elaine Zhang Cc: mturquette@baylibre.com, sboyd@codeaurora.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, huangtao@rock-chips.com, cl@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com Subject: Re: [PATCH v1] clk: fractional-divider: fix up the fractional clk's jitter Date: Thu, 06 Jul 2017 12:01:47 +0200 Message-ID: <1526168.oPMo9mtzVm@diego> User-Agent: KMail/5.2.3 (Linux/4.8.0-2-amd64; KDE/5.27.0; x86_64; ; ) In-Reply-To: <1499329714-24119-1-git-send-email-zhangqing@rock-chips.com> References: <1499329714-24119-1-git-send-email-zhangqing@rock-chips.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Elaine, Am Donnerstag, 6. Juli 2017, 16:28:34 CEST schrieb Elaine Zhang: > fractional divider must set that denominator is 20 times larger than > numerator to generate precise clock frequency. > Otherwise the CLK jitter is very big, poor quality of the clock signal. > > RK document description: > 3.1.9 Fractional divider usage > To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by > fractional divider. Generally you must set that denominator is 20 times > larger than numerator to generate precise clock frequency. So the > fractional divider applies only to generate low frequency clock like > I2S, UART. > > Signed-off-by: Elaine Zhang > --- > drivers/clk/clk-fractional-divider.c | 13 +++++++++++++ As I said in our previous private mails, having soc-specific quirks in the generic driver won't work. I just realized that while I mentioned a different approach in one my mails, I seem to have forgotten to attach the patch showcasing my idea. [Just realized that while looking at the old mails] Sorry about that. So the idea would be allowing clk-fractional users to just provide their own approximation function, which you could then provide one for the rockchip-specific requirements. That change was only compile- tested at the time, so you might want to check if it actually works, For the below you would "just" need to create an approximation function and adapt the rockchip_clk_register_frac_branch to set div->approx to your approximation function. Heiko --------- From: Heiko Stuebner Date: Fri, 2 Jun 2017 13:42:51 +0200 Subject: [PATCH] clk: fractional-divider: allow clk-specific approximation functions Fractional dividers may have special requirements concerning numerator and denominator selection that differ from just getting the best approximation. For example on Rockchip socs the denominator must be at least 20 times larger than the numerator to generate precise clock frequencies. Therefore add the ability to provide custom approximation functions but fall back to rational_best_approximation in the default case. Signed-off-by: Heiko Stuebner --- drivers/clk/clk-fractional-divider.c | 42 ++++++++++++++++++++++++++++++++---- include/linux/clk-provider.h | 17 +++++++++++++++ 2 files changed, 55 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index aab904618eb6..2a066d8182e1 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -69,7 +69,7 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate, if (scale > fd->nwidth) rate <<= scale - fd->nwidth; - rational_best_approximation(rate, *parent_rate, + fd->approx(rate, *parent_rate, GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), &m, &n); @@ -87,7 +87,7 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long m, n; u32 val; - rational_best_approximation(rate, parent_rate, + fd->approx(rate, parent_rate, GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), &m, &n); @@ -116,10 +116,13 @@ const struct clk_ops clk_fractional_divider_ops = { }; EXPORT_SYMBOL_GPL(clk_fractional_divider_ops); -struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, +struct clk_hw *clk_hw_register_fractional_divider_custom(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, - u8 clk_divider_flags, spinlock_t *lock) + u8 clk_divider_flags, spinlock_t *lock, void (*approx) + (unsigned long gnum, unsigned long gdenom, + unsigned long mnum, unsigned long mdenom, + unsigned long *bnum, unsigned long *bdenom)) { struct clk_fractional_divider *fd; struct clk_init_data init; @@ -145,6 +148,7 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, fd->nmask = GENMASK(nwidth - 1, 0) << nshift; fd->flags = clk_divider_flags; fd->lock = lock; + fd->approx = approx; fd->hw.init = &init; hw = &fd->hw; @@ -156,8 +160,38 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, return hw; } +EXPORT_SYMBOL_GPL(clk_hw_register_fractional_divider_custom); + +struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, + u8 clk_divider_flags, spinlock_t *lock) +{ + return clk_hw_register_fractional_divider_custom(dev, name, parent_name, + flags, reg, mshift, mwidth, nshift, nwidth, clk_divider_flags, + lock, rational_best_approximation); +} EXPORT_SYMBOL_GPL(clk_hw_register_fractional_divider); +struct clk *clk_register_fractional_divider_custom(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, + u8 clk_divider_flags, spinlock_t *lock, void (*approx) + (unsigned long gnum, unsigned long gdenom, + unsigned long mnum, unsigned long mdenom, + unsigned long *bnum, unsigned long *bdenom)) +{ + struct clk_hw *hw; + + hw = clk_hw_register_fractional_divider_custom(dev, name, parent_name, + flags, reg, mshift, mwidth, nshift, nwidth, + clk_divider_flags, lock, approx); + if (IS_ERR(hw)) + return ERR_CAST(hw); + return hw->clk; +} +EXPORT_SYMBOL_GPL(clk_register_fractional_divider_custom); + struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index a428aec36ace..5bf2bc49ccb7 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -564,16 +564,33 @@ struct clk_fractional_divider { u8 nwidth; u32 nmask; u8 flags; + void (*approx)(unsigned long gnum, unsigned long gdenom, + unsigned long mnum, unsigned long mdenom, + unsigned long *bnum, unsigned long *bdenom); spinlock_t *lock; }; #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) extern const struct clk_ops clk_fractional_divider_ops; +struct clk *clk_register_fractional_divider_custom(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, + u8 clk_divider_flags, spinlock_t *lock, void (*approx) + (unsigned long gnum, unsigned long gdenom, + unsigned long mnum, unsigned long mdenom, + unsigned long *bnum, unsigned long *bdenom)); struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock); +struct clk_hw *clk_hw_register_fractional_divider_custom(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, + u8 clk_divider_flags, spinlock_t *lock, void (*approx) + (unsigned long gnum, unsigned long gdenom, + unsigned long mnum, unsigned long mdenom, + unsigned long *bnum, unsigned long *bdenom)); struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,